Optimization of the merged transistor logic gate.
Thesis: M.S., Massachusetts Institute of Technology, Department of Electrical Engineering, 1973
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| Format: | Thesis |
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Massachusetts Institute of Technology
2023
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| Online Access: | https://hdl.handle.net/1721.1/151780 |
| _version_ | 1826203401651748864 |
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| author | Kling, Gary William. |
| author2 | Massachusetts Institute of Technology. Department of Electrical Engineering |
| author_facet | Massachusetts Institute of Technology. Department of Electrical Engineering Kling, Gary William. |
| author_sort | Kling, Gary William. |
| collection | MIT |
| description | Thesis: M.S., Massachusetts Institute of Technology, Department of Electrical Engineering, 1973 |
| first_indexed | 2024-09-23T12:36:23Z |
| format | Thesis |
| id | mit-1721.1/151780 |
| institution | Massachusetts Institute of Technology |
| last_indexed | 2024-09-23T12:36:23Z |
| publishDate | 2023 |
| publisher | Massachusetts Institute of Technology |
| record_format | dspace |
| spelling | mit-1721.1/1517802023-08-22T03:27:29Z Optimization of the merged transistor logic gate. Kling, Gary William. Massachusetts Institute of Technology. Department of Electrical Engineering Electrical Engineering Thesis: M.S., Massachusetts Institute of Technology, Department of Electrical Engineering, 1973 Includes bibliographical references. M.S. M.S. Massachusetts Institute of Technology, Department of Electrical Engineering 2023-08-21T16:24:12Z 2023-08-21T16:24:12Z 1973 1973 Thesis https://hdl.handle.net/1721.1/151780 24352054 MIT theses may be protected by copyright. Please reuse MIT thesis content according to the MIT Libraries Permissions Policy, which is available through the URL provided. http://dspace.mit.edu/handle/1721.1/7582 96 leaves application/pdf Massachusetts Institute of Technology |
| spellingShingle | Electrical Engineering Kling, Gary William. Optimization of the merged transistor logic gate. |
| title | Optimization of the merged transistor logic gate. |
| title_full | Optimization of the merged transistor logic gate. |
| title_fullStr | Optimization of the merged transistor logic gate. |
| title_full_unstemmed | Optimization of the merged transistor logic gate. |
| title_short | Optimization of the merged transistor logic gate. |
| title_sort | optimization of the merged transistor logic gate |
| topic | Electrical Engineering |
| url | https://hdl.handle.net/1721.1/151780 |
| work_keys_str_mv | AT klinggarywilliam optimizationofthemergedtransistorlogicgate |