A Secure Digital In-Memory Compute (IMC) Macro with Protections for Side-Channel and Bus Probing Attacks

2024 IEEE Custom Integrated Circuits Conference April 21st – 24th, 2024 Denver, CO U.S.

Bibliographic Details
Main Authors: Ashok, Maitreyi, Maji, Saurav, Zhang, Xin, Cohn, John, Chandrakasan, Anantha P.
Other Authors: Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Format: Article
Published: IEEE 2024
Online Access:https://hdl.handle.net/1721.1/154299
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author Ashok, Maitreyi
Maji, Saurav
Zhang, Xin
Cohn, John
Chandrakasan, Anantha P.
author2 Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
author_facet Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Ashok, Maitreyi
Maji, Saurav
Zhang, Xin
Cohn, John
Chandrakasan, Anantha P.
author_sort Ashok, Maitreyi
collection MIT
description 2024 IEEE Custom Integrated Circuits Conference April 21st – 24th, 2024 Denver, CO U.S.
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spelling mit-1721.1/1542992024-12-23T06:29:57Z A Secure Digital In-Memory Compute (IMC) Macro with Protections for Side-Channel and Bus Probing Attacks Ashok, Maitreyi Maji, Saurav Zhang, Xin Cohn, John Chandrakasan, Anantha P. Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science 2024 IEEE Custom Integrated Circuits Conference April 21st – 24th, 2024 Denver, CO U.S. Machine learning (ML) accelerators provide energy efficient neural network (NN) implementations for applications such as speech recognition and image processing. Recently, digital IMC has been proposed to reduce data transfer energy, while still allowing for higher bitwidths and accuracies necessary for many workloads, especially with technology scaling [1,2]. Privacy of ML workloads can be exploited with physical side-channel attacks (SCAs) or bus probing attacks (BPAs) [3] (Fig. 1). While SCAs correlate IC power consumption or EM emissions to data or operations, BPAs directly tap traces between the IC and off-chip memory. The inputs reflect private data collected on IoT devices, such as images of faces. The weights, typically stored off-chip, reveal information about proprietary private training datasets. This work presents the first IMC macro protected against SCAs and BPAs to mitigate these risks. National Science Foundation (NSF) MIT-IBM Watson AI Lab, MathWorks Engineering Fellowship 2024-04-26T14:47:37Z 2024-04-26T14:47:37Z 2024-04 Article http://purl.org/eprint/type/ConferencePaper https://hdl.handle.net/1721.1/154299 Ashok, Maitreyi, Maji, Saurav, Zhang, Xin, Cohn, John and Chandrakasan, Anantha P. 2024. "A Secure Digital In-Memory Compute (IMC) Macro with Protections for Side-Channel and Bus Probing Attacks." Creative Commons Attribution-Noncommercial-ShareAlike http://creativecommons.org/licenses/by-nc-sa/4.0/ application/pdf IEEE Author
spellingShingle Ashok, Maitreyi
Maji, Saurav
Zhang, Xin
Cohn, John
Chandrakasan, Anantha P.
A Secure Digital In-Memory Compute (IMC) Macro with Protections for Side-Channel and Bus Probing Attacks
title A Secure Digital In-Memory Compute (IMC) Macro with Protections for Side-Channel and Bus Probing Attacks
title_full A Secure Digital In-Memory Compute (IMC) Macro with Protections for Side-Channel and Bus Probing Attacks
title_fullStr A Secure Digital In-Memory Compute (IMC) Macro with Protections for Side-Channel and Bus Probing Attacks
title_full_unstemmed A Secure Digital In-Memory Compute (IMC) Macro with Protections for Side-Channel and Bus Probing Attacks
title_short A Secure Digital In-Memory Compute (IMC) Macro with Protections for Side-Channel and Bus Probing Attacks
title_sort secure digital in memory compute imc macro with protections for side channel and bus probing attacks
url https://hdl.handle.net/1721.1/154299
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