Formally Verifying a Programmable Network Switch
Programmable network switches are complex pieces of hardware that leverage nonobvious optimizations such as pipelining to offer flexible configuration interfaces. In this thesis, we propose a novel formal-verification methodology aimed at establishing strong correctness theorems for synthesizable ha...
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| Format: | Thesis |
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Massachusetts Institute of Technology
2024
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| Online Access: | https://hdl.handle.net/1721.1/156273 |
| _version_ | 1811071006374100992 |
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| author | Liu, Jiazheng |
| author2 | Chlipala, Adam |
| author_facet | Chlipala, Adam Liu, Jiazheng |
| author_sort | Liu, Jiazheng |
| collection | MIT |
| description | Programmable network switches are complex pieces of hardware that leverage nonobvious optimizations such as pipelining to offer flexible configuration interfaces. In this thesis, we propose a novel formal-verification methodology aimed at establishing strong correctness theorems for synthesizable hardware designs for network functionality, demonstrated through a case-study analysis of a Tofino-like programmable switch that we call VeriSwit. Our approach hinges on modularity, whereby the system is split into interconnected units, each equipped with its specification and proof, oblivious to the internals of other units. We conduct VeriSwit’s modular verification in the Coq theorem prover. Experiments with synthesis for both FPGA and ASIC targets, combined with simulation, show that 100 GB/s line rate is easily achieved. |
| first_indexed | 2024-09-23T08:44:39Z |
| format | Thesis |
| id | mit-1721.1/156273 |
| institution | Massachusetts Institute of Technology |
| last_indexed | 2024-09-23T08:44:39Z |
| publishDate | 2024 |
| publisher | Massachusetts Institute of Technology |
| record_format | dspace |
| spelling | mit-1721.1/1562732024-08-22T03:59:53Z Formally Verifying a Programmable Network Switch Liu, Jiazheng Chlipala, Adam Arvind Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science Programmable network switches are complex pieces of hardware that leverage nonobvious optimizations such as pipelining to offer flexible configuration interfaces. In this thesis, we propose a novel formal-verification methodology aimed at establishing strong correctness theorems for synthesizable hardware designs for network functionality, demonstrated through a case-study analysis of a Tofino-like programmable switch that we call VeriSwit. Our approach hinges on modularity, whereby the system is split into interconnected units, each equipped with its specification and proof, oblivious to the internals of other units. We conduct VeriSwit’s modular verification in the Coq theorem prover. Experiments with synthesis for both FPGA and ASIC targets, combined with simulation, show that 100 GB/s line rate is easily achieved. S.M. 2024-08-21T18:53:03Z 2024-08-21T18:53:03Z 2024-05 2024-07-10T12:59:44.755Z Thesis https://hdl.handle.net/1721.1/156273 In Copyright - Educational Use Permitted Copyright retained by author(s) https://rightsstatements.org/page/InC-EDU/1.0/ application/pdf Massachusetts Institute of Technology |
| spellingShingle | Liu, Jiazheng Formally Verifying a Programmable Network Switch |
| title | Formally Verifying a Programmable Network Switch |
| title_full | Formally Verifying a Programmable Network Switch |
| title_fullStr | Formally Verifying a Programmable Network Switch |
| title_full_unstemmed | Formally Verifying a Programmable Network Switch |
| title_short | Formally Verifying a Programmable Network Switch |
| title_sort | formally verifying a programmable network switch |
| url | https://hdl.handle.net/1721.1/156273 |
| work_keys_str_mv | AT liujiazheng formallyverifyingaprogrammablenetworkswitch |