High-level automatic pipelining for sequential circuits

This paper presents a new approach for automatically pipelining sequential circuits. The approach repeatedly extracts a computation from the critical path, moves it into a new stage, then uses speculation to generate a stream of values that keep the pipeline full. The newly generated circuit retains...

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Main Authors: Marinescu, Maria-Cristina V, Rinard, Martin
Other Authors: Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory
Format: Article
Language:English
Published: ACM Press 2025
Online Access:https://hdl.handle.net/1721.1/158090
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author Marinescu, Maria-Cristina V
Rinard, Martin
author2 Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory
author_facet Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory
Marinescu, Maria-Cristina V
Rinard, Martin
author_sort Marinescu, Maria-Cristina V
collection MIT
description This paper presents a new approach for automatically pipelining sequential circuits. The approach repeatedly extracts a computation from the critical path, moves it into a new stage, then uses speculation to generate a stream of values that keep the pipeline full. The newly generated circuit retains enough state to recover from incorrect speculations by flushing the incorrect values from the pipeline, restoring the correct state, then restarting the computation. We also implement two extensions to this basic approach: stalling, which minimizes circuit area by eliminating speculation, and forwarding, which increases the throughput of the generated circuit by forwarding correct values to preceding pipeline stages. We have implemented a prototype synthesizer based on this approach. Our experimental results show that, starting with a non-pipelined or insufficiently pipelined specification, this synthesizer can effectively reduce the clock cycle time and improve the throughput of the generated circuit.
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spelling mit-1721.1/1580902025-02-13T19:19:11Z High-level automatic pipelining for sequential circuits Marinescu, Maria-Cristina V Rinard, Martin Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory This paper presents a new approach for automatically pipelining sequential circuits. The approach repeatedly extracts a computation from the critical path, moves it into a new stage, then uses speculation to generate a stream of values that keep the pipeline full. The newly generated circuit retains enough state to recover from incorrect speculations by flushing the incorrect values from the pipeline, restoring the correct state, then restarting the computation. We also implement two extensions to this basic approach: stalling, which minimizes circuit area by eliminating speculation, and forwarding, which increases the throughput of the generated circuit by forwarding correct values to preceding pipeline stages. We have implemented a prototype synthesizer based on this approach. Our experimental results show that, starting with a non-pipelined or insufficiently pipelined specification, this synthesizer can effectively reduce the clock cycle time and improve the throughput of the generated circuit. 2025-01-28T16:23:51Z 2025-01-28T16:23:51Z 2001 2025-01-28T16:20:59Z Article http://purl.org/eprint/type/ConferencePaper https://hdl.handle.net/1721.1/158090 Marinescu, Maria-Cristina V and Rinard, Martin. 2001. "High-level automatic pipelining for sequential circuits." Proceedings of the 14th international symposium on Systems synthesis - ISSS '01. en 10.1145/500001.500053 Proceedings of the 14th international symposium on Systems synthesis - ISSS '01 Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use. application/pdf ACM Press 495978
spellingShingle Marinescu, Maria-Cristina V
Rinard, Martin
High-level automatic pipelining for sequential circuits
title High-level automatic pipelining for sequential circuits
title_full High-level automatic pipelining for sequential circuits
title_fullStr High-level automatic pipelining for sequential circuits
title_full_unstemmed High-level automatic pipelining for sequential circuits
title_short High-level automatic pipelining for sequential circuits
title_sort high level automatic pipelining for sequential circuits
url https://hdl.handle.net/1721.1/158090
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