High-level specification and efficient implementation of pipelined circuits
© 2001 IEEE. This paper describes a novel approach to high-level synthesis of complex pipelined circuits, including pipelined circuits with feedback. This approach combines a high-level, modular specification language with an efficient implementation. In our system, the designer specifies the circui...
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| Format: | Article |
| Language: | English |
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IEEE
2025
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| Online Access: | https://hdl.handle.net/1721.1/158093 |
| _version_ | 1824458030574469120 |
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| author | Marinescu, M-C Rinard, M |
| author2 | Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory |
| author_facet | Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory Marinescu, M-C Rinard, M |
| author_sort | Marinescu, M-C |
| collection | MIT |
| description | © 2001 IEEE. This paper describes a novel approach to high-level synthesis of complex pipelined circuits, including pipelined circuits with feedback. This approach combines a high-level, modular specification language with an efficient implementation. In our system, the designer specifies the circuit as a set of independent modules connected by conceptually unbounded queues. Our synthesis algorithm automatically transforms this modular, asynchronous specification into a tightly coupled, fully synchronous implementation in synthesizable Verilog. |
| first_indexed | 2025-02-19T04:19:25Z |
| format | Article |
| id | mit-1721.1/158093 |
| institution | Massachusetts Institute of Technology |
| language | English |
| last_indexed | 2025-02-19T04:19:25Z |
| publishDate | 2025 |
| publisher | IEEE |
| record_format | dspace |
| spelling | mit-1721.1/1580932025-02-13T19:19:55Z High-level specification and efficient implementation of pipelined circuits Marinescu, M-C Rinard, M Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory © 2001 IEEE. This paper describes a novel approach to high-level synthesis of complex pipelined circuits, including pipelined circuits with feedback. This approach combines a high-level, modular specification language with an efficient implementation. In our system, the designer specifies the circuit as a set of independent modules connected by conceptually unbounded queues. Our synthesis algorithm automatically transforms this modular, asynchronous specification into a tightly coupled, fully synchronous implementation in synthesizable Verilog. 2025-01-28T16:42:17Z 2025-01-28T16:42:17Z 2001-01-01 2025-01-28T16:39:44Z Article http://purl.org/eprint/type/ConferencePaper https://hdl.handle.net/1721.1/158093 High-Level Specification and Efficient Implementation of Pipelined Circuits. Asia and South Pacific Design Automation Conference 2001, ASP-DAC 2001, January 30, 2001 - February 2, 2001. 2001. Institute of Electrical and Electronics Engineers Inc. en 10.1109/aspdac.2001.913384 Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455) Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use. application/pdf IEEE Marinescu |
| spellingShingle | Marinescu, M-C Rinard, M High-level specification and efficient implementation of pipelined circuits |
| title | High-level specification and efficient implementation of pipelined circuits |
| title_full | High-level specification and efficient implementation of pipelined circuits |
| title_fullStr | High-level specification and efficient implementation of pipelined circuits |
| title_full_unstemmed | High-level specification and efficient implementation of pipelined circuits |
| title_short | High-level specification and efficient implementation of pipelined circuits |
| title_sort | high level specification and efficient implementation of pipelined circuits |
| url | https://hdl.handle.net/1721.1/158093 |
| work_keys_str_mv | AT marinescumc highlevelspecificationandefficientimplementationofpipelinedcircuits AT rinardm highlevelspecificationandefficientimplementationofpipelinedcircuits |