SySTeC: A Symmetric Sparse Tensor Compiler

SySTeC: A Symmetric Sparse Tensor Compiler

CGO ’25, March 01–05, 2025, Las Vegas, NV, USA

Bibliographic Details
Main Authors: Patel, Radha, Ahrens, Willow, Amarasinghe, Saman
Other Authors: Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory
Format: Article
Language:English
Published: ACM|Proceedings of the 23rd ACM/IEEE International Symposium on Code Generation and Optimization 2025
Online Access:https://hdl.handle.net/1721.1/158438

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