A PCI Express to PCIX Bridge optimized for performance and area
Thesis (M. Eng. and S.B.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, June 2004.
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| Format: | Thesis |
| Language: | eng |
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Massachusetts Institute of Technology
2005
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| Online Access: | http://hdl.handle.net/1721.1/16674 |
| _version_ | 1826213788935782400 |
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| author | Chong, Margaret J. (Margaret Jane), 1981- |
| author2 | Peter J. Jenkins , Jeffrey LaFramboise and Christopher J. Terman. |
| author_facet | Peter J. Jenkins , Jeffrey LaFramboise and Christopher J. Terman. Chong, Margaret J. (Margaret Jane), 1981- |
| author_sort | Chong, Margaret J. (Margaret Jane), 1981- |
| collection | MIT |
| description | Thesis (M. Eng. and S.B.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, June 2004. |
| first_indexed | 2024-09-23T15:54:51Z |
| format | Thesis |
| id | mit-1721.1/16674 |
| institution | Massachusetts Institute of Technology |
| language | eng |
| last_indexed | 2024-09-23T15:54:51Z |
| publishDate | 2005 |
| publisher | Massachusetts Institute of Technology |
| record_format | dspace |
| spelling | mit-1721.1/166742019-04-10T13:42:27Z A PCI Express to PCIX Bridge optimized for performance and area Chong, Margaret J. (Margaret Jane), 1981- Peter J. Jenkins , Jeffrey LaFramboise and Christopher J. Terman. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Electrical Engineering and Computer Science. PCI bus (Computer bus) Thesis (M. Eng. and S.B.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, June 2004. Includes bibliographical references (leaf 89). This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections. This thesis project involves the architecture, implementation, and verification of a high bandwidth, low cost ASIC digital logic core that is compliant with the PCI Express to PCIX Bridge Specification. The core supports PCI Express and PCIX transactions, x16 PCI Express link widths, 32 and 64-bit PCIX link widths, all PCI Express and PCIX packet sizes, transaction ordering and queuing, relaxed ordering, flow control, and buffer management. Performance and area are optimized at the architectural and logic levels. The core is approximately 27K gate count, runs at a maximum of 250 MHz, and is synthesized to a current standard technology. This thesis explores PCI Express, PCIX, and PCI technologies, architectural design, development of Verilog and Vera models, thorough module-level verification, the development of a PCI Express/PCIX system verification environment, synthesis, static timing analysis, and performance and area evaluations. The work has been completed in IBM Microelectronics in Burlington, Vermont as part of the MIT VI-A Program. by Margaret J. Chong. M.Eng.and S.B. 2005-05-17T14:53:12Z 2005-05-17T14:53:12Z 2003 2004 Thesis http://hdl.handle.net/1721.1/16674 56823037 eng M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 89 leaves 1534220 bytes 1611421 bytes application/pdf application/pdf application/pdf Massachusetts Institute of Technology |
| spellingShingle | Electrical Engineering and Computer Science. PCI bus (Computer bus) Chong, Margaret J. (Margaret Jane), 1981- A PCI Express to PCIX Bridge optimized for performance and area |
| title | A PCI Express to PCIX Bridge optimized for performance and area |
| title_full | A PCI Express to PCIX Bridge optimized for performance and area |
| title_fullStr | A PCI Express to PCIX Bridge optimized for performance and area |
| title_full_unstemmed | A PCI Express to PCIX Bridge optimized for performance and area |
| title_short | A PCI Express to PCIX Bridge optimized for performance and area |
| title_sort | pci express to pcix bridge optimized for performance and area |
| topic | Electrical Engineering and Computer Science. PCI bus (Computer bus) |
| url | http://hdl.handle.net/1721.1/16674 |
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