Wire delay models for global placement of ASICs
Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2002.
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| Format: | Thesis |
| Language: | eng |
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Massachusetts Institute of Technology
2005
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| Online Access: | http://hdl.handle.net/1721.1/16855 |
| _version_ | 1826213391614607360 |
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| author | Paskalev, Krassimir (Krassimir Ivanov), 1978- |
| author2 | Michael Fu and Jacob K. White. |
| author_facet | Michael Fu and Jacob K. White. Paskalev, Krassimir (Krassimir Ivanov), 1978- |
| author_sort | Paskalev, Krassimir (Krassimir Ivanov), 1978- |
| collection | MIT |
| description | Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2002. |
| first_indexed | 2024-09-23T15:48:21Z |
| format | Thesis |
| id | mit-1721.1/16855 |
| institution | Massachusetts Institute of Technology |
| language | eng |
| last_indexed | 2024-09-23T15:48:21Z |
| publishDate | 2005 |
| publisher | Massachusetts Institute of Technology |
| record_format | dspace |
| spelling | mit-1721.1/168552019-04-12T17:11:21Z Wire delay models for global placement of ASICs Wire delay models for global placement of Application-Specific Integrated Circuits Paskalev, Krassimir (Krassimir Ivanov), 1978- Michael Fu and Jacob K. White. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Electrical Engineering and Computer Science. Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2002. Includes bibliographical references (leaves 28-29). This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections. A new model for the propagation delay between two logic gates for timing-driven global placement is proposed. The model is a function of the number of pins on the net, the half perimeter of the bounding box enclosing the net, and the half perimeter of the bounding box enclosing the driving pin and the sink pin. On a training set of two designs and testing set of another two, the proposed model is 31% more accurate than the current state-of-the-art model and has comparable computational complexity. by Krassimir Paskalev. M.Eng. 2005-05-19T15:02:20Z 2005-05-19T15:02:20Z 2002 2002 Thesis http://hdl.handle.net/1721.1/16855 51588096 eng M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 29 leaves 475019 bytes 474775 bytes application/pdf application/pdf application/pdf Massachusetts Institute of Technology |
| spellingShingle | Electrical Engineering and Computer Science. Paskalev, Krassimir (Krassimir Ivanov), 1978- Wire delay models for global placement of ASICs |
| title | Wire delay models for global placement of ASICs |
| title_full | Wire delay models for global placement of ASICs |
| title_fullStr | Wire delay models for global placement of ASICs |
| title_full_unstemmed | Wire delay models for global placement of ASICs |
| title_short | Wire delay models for global placement of ASICs |
| title_sort | wire delay models for global placement of asics |
| topic | Electrical Engineering and Computer Science. |
| url | http://hdl.handle.net/1721.1/16855 |
| work_keys_str_mv | AT paskalevkrassimirkrassimirivanov1978 wiredelaymodelsforglobalplacementofasics AT paskalevkrassimirkrassimirivanov1978 wiredelaymodelsforglobalplacementofapplicationspecificintegratedcircuits |