Hardware implementation of a low-power two-dimensional discrete cosine transform
Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2002.
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| Format: | Thesis |
| Language: | eng |
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Massachusetts Institute of Technology
2005
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| Online Access: | http://hdl.handle.net/1721.1/16859 |
| _version_ | 1826205440615120896 |
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| author | Shah, Rajul R. (Rajul Ramesh), 1979- |
| author2 | Richard E. Anderson and Anantha P. Chandrakasan. |
| author_facet | Richard E. Anderson and Anantha P. Chandrakasan. Shah, Rajul R. (Rajul Ramesh), 1979- |
| author_sort | Shah, Rajul R. (Rajul Ramesh), 1979- |
| collection | MIT |
| description | Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2002. |
| first_indexed | 2024-09-23T13:12:50Z |
| format | Thesis |
| id | mit-1721.1/16859 |
| institution | Massachusetts Institute of Technology |
| language | eng |
| last_indexed | 2024-09-23T13:12:50Z |
| publishDate | 2005 |
| publisher | Massachusetts Institute of Technology |
| record_format | dspace |
| spelling | mit-1721.1/168592019-04-11T01:58:28Z Hardware implementation of a low-power two-dimensional discrete cosine transform Shah, Rajul R. (Rajul Ramesh), 1979- Richard E. Anderson and Anantha P. Chandrakasan. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Electrical Engineering and Computer Science. Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2002. Includes bibliographical references (p. 143-144). This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections. In this project, a JPEG compliant, low-power dedicated, two-dimensional, Discrete Cosine Transform (DCT) core meeting all IBM Softcore requirements is developed. Power is optimized completely at the algorithmic, architectural, and logic levels. The architecture uses row-column decomposition of a fast 1-D algorithm implemented with distributed arithmetic. It features clock gating schemes as well as power-aware schemes that utilize input correlations to dynamically scale down power consumption. This is done by eliminating glitching in the ROM Accumulate (RAC) units to effectively stop unnecessary computation. The core is approximately 180K transistors, runs at a maximum of 100MHz, is synthesized to a .18[mu]m double-well CMOS technology with a 1.8V power supply, and consumes between 63 and 87 mW of power at 100MHz depending on the image data. The thesis explores the algorithmic evaluations, architectural design, development of the C and VHDL models, verification methods, synthesis operations, static timing analysis, design for test compliance, power analysis, and performance comparisons for the development of the core. The work has been completed in the ASIC Digital Cores I department of the IBM Microelectronics Division in Burlington, Vermont as part of the third assignment in the MIT VI-A program. by Rajul R. Shah. M.Eng. 2005-05-19T15:03:10Z 2005-05-19T15:03:10Z 2002 2002 Thesis http://hdl.handle.net/1721.1/16859 51619520 eng M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 144 p. 629721 bytes 629478 bytes application/pdf application/pdf application/pdf Massachusetts Institute of Technology |
| spellingShingle | Electrical Engineering and Computer Science. Shah, Rajul R. (Rajul Ramesh), 1979- Hardware implementation of a low-power two-dimensional discrete cosine transform |
| title | Hardware implementation of a low-power two-dimensional discrete cosine transform |
| title_full | Hardware implementation of a low-power two-dimensional discrete cosine transform |
| title_fullStr | Hardware implementation of a low-power two-dimensional discrete cosine transform |
| title_full_unstemmed | Hardware implementation of a low-power two-dimensional discrete cosine transform |
| title_short | Hardware implementation of a low-power two-dimensional discrete cosine transform |
| title_sort | hardware implementation of a low power two dimensional discrete cosine transform |
| topic | Electrical Engineering and Computer Science. |
| url | http://hdl.handle.net/1721.1/16859 |
| work_keys_str_mv | AT shahrajulrrajulramesh1979 hardwareimplementationofalowpowertwodimensionaldiscretecosinetransform |