Efficient pipelining of nested loops : unroll-and-squash
Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2001.
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| Format: | Thesis |
| Language: | eng |
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Massachusetts Institute of Technology
2005
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| Online Access: | http://hdl.handle.net/1721.1/16861 |
| _version_ | 1826214628441456640 |
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| author | Petkov, Darin S. (Darin Stamenov), 1977- |
| author2 | Randolph E. Harr and Saman P. Amarasinghe. |
| author_facet | Randolph E. Harr and Saman P. Amarasinghe. Petkov, Darin S. (Darin Stamenov), 1977- |
| author_sort | Petkov, Darin S. (Darin Stamenov), 1977- |
| collection | MIT |
| description | Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2001. |
| first_indexed | 2024-09-23T16:08:31Z |
| format | Thesis |
| id | mit-1721.1/16861 |
| institution | Massachusetts Institute of Technology |
| language | eng |
| last_indexed | 2024-09-23T16:08:31Z |
| publishDate | 2005 |
| publisher | Massachusetts Institute of Technology |
| record_format | dspace |
| spelling | mit-1721.1/168612019-04-10T21:39:40Z Efficient pipelining of nested loops : unroll-and-squash Petkov, Darin S. (Darin Stamenov), 1977- Randolph E. Harr and Saman P. Amarasinghe. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Electrical Engineering and Computer Science. Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2001. Includes bibliographical references (leaves 49-50). This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections. The size and complexity of current custom VLSI have forced the use of high-level programming languages to describe hardware, and compiler and synthesis technology to map abstract designs into silicon. Many applications operating on large streaming data usually require a custom VLSI because of high performance or low power restrictions. Since the data processing is typically described by loop constructs in a high-level language, loops are the most critical portions of the hardware description and special techniques are developed to optimally synthesize them. In this thesis, we introduce a new method for mapping nested loops into hardware and pipelining them efficiently. The technique achieves fine-grain parallelism even on strong intra- and inter-iteration data-dependent inner loops and, by economically sharing resources, improves performance at the expense of a small amount of additional area. We implemented the transformation within the Nimble Compiler environment and evaluated its performance on several signal-processing benchmarks. The method achieves up to 2x increase in the area efficiency compared to the best known optimization techniques. by Darin S. Petkov. M.Eng. 2005-05-19T15:03:35Z 2005-05-19T15:03:35Z 2001 2001 Thesis http://hdl.handle.net/1721.1/16861 51626122 eng M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 50 leaves 211181 bytes 210937 bytes application/pdf application/pdf application/pdf Massachusetts Institute of Technology |
| spellingShingle | Electrical Engineering and Computer Science. Petkov, Darin S. (Darin Stamenov), 1977- Efficient pipelining of nested loops : unroll-and-squash |
| title | Efficient pipelining of nested loops : unroll-and-squash |
| title_full | Efficient pipelining of nested loops : unroll-and-squash |
| title_fullStr | Efficient pipelining of nested loops : unroll-and-squash |
| title_full_unstemmed | Efficient pipelining of nested loops : unroll-and-squash |
| title_short | Efficient pipelining of nested loops : unroll-and-squash |
| title_sort | efficient pipelining of nested loops unroll and squash |
| topic | Electrical Engineering and Computer Science. |
| url | http://hdl.handle.net/1721.1/16861 |
| work_keys_str_mv | AT petkovdarinsdarinstamenov1977 efficientpipeliningofnestedloopsunrollandsquash |