High speed DSP implementation in run-time partially reconfigurable FPGAs
Thesis (M.Eng. and S.B.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2003.
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| Format: | Thesis |
| Language: | eng |
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Massachusetts Institute of Technology
2005
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| Online Access: | http://hdl.handle.net/1721.1/16982 |
| _version_ | 1811088100651171840 |
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| author | McBride, Justin D. (Justin Donald), 1980- |
| author2 | Sean Adam and Christopher Terman. |
| author_facet | Sean Adam and Christopher Terman. McBride, Justin D. (Justin Donald), 1980- |
| author_sort | McBride, Justin D. (Justin Donald), 1980- |
| collection | MIT |
| description | Thesis (M.Eng. and S.B.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2003. |
| first_indexed | 2024-09-23T13:56:16Z |
| format | Thesis |
| id | mit-1721.1/16982 |
| institution | Massachusetts Institute of Technology |
| language | eng |
| last_indexed | 2024-09-23T13:56:16Z |
| publishDate | 2005 |
| publisher | Massachusetts Institute of Technology |
| record_format | dspace |
| spelling | mit-1721.1/169822019-04-11T14:05:58Z High speed DSP implementation in run-time partially reconfigurable FPGAs High speed digital signal processing implementation in run-time partially reconfigurable field programmable gate arrays McBride, Justin D. (Justin Donald), 1980- Sean Adam and Christopher Terman. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Electrical Engineering and Computer Science. Signal processing Digital techniques Field programmable gate arrays Thesis (M.Eng. and S.B.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2003. Includes bibliographical references (leaves 99-100). This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections. This thesis investigates the feasibility of utilizing a run-time partially reconfigurable FPGA to implement a sequence of high-speed digital signal processing filters. Rather than reconfiguring the entire device to modify part of a configuration, a modular architecture is designed to allow smaller segments of the device to be individually reconfigured while the remainder of the device continues to operate. This document describes the design, implementation, simulation, and benchmarking of a five-socket modular DSP architecture and compares the results to the performance of alternative digital signal processing methods, particularly that of software DSP subroutines run on a PowerPC processor. The result is a highly flexible architecture that supports the use of timing verified hardware subroutines that could be partially reconfigured onto the FPGA within 3ms. The highly parallel processing power of the FPGA design yields a performance of 5.825 billion multiply and accumulate operations per second while simulated running at 72.8MHz, more than 76 times faster than similar calculations measured on a MPC7410 processor. by Justin D. McBride. M.Eng.and S.B. 2005-05-19T15:32:04Z 2005-05-19T15:32:04Z 2003 2003 Thesis http://hdl.handle.net/1721.1/16982 53884295 eng M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 100 leaves 550878 bytes 551330 bytes application/pdf application/pdf application/pdf Massachusetts Institute of Technology |
| spellingShingle | Electrical Engineering and Computer Science. Signal processing Digital techniques Field programmable gate arrays McBride, Justin D. (Justin Donald), 1980- High speed DSP implementation in run-time partially reconfigurable FPGAs |
| title | High speed DSP implementation in run-time partially reconfigurable FPGAs |
| title_full | High speed DSP implementation in run-time partially reconfigurable FPGAs |
| title_fullStr | High speed DSP implementation in run-time partially reconfigurable FPGAs |
| title_full_unstemmed | High speed DSP implementation in run-time partially reconfigurable FPGAs |
| title_short | High speed DSP implementation in run-time partially reconfigurable FPGAs |
| title_sort | high speed dsp implementation in run time partially reconfigurable fpgas |
| topic | Electrical Engineering and Computer Science. Signal processing Digital techniques Field programmable gate arrays |
| url | http://hdl.handle.net/1721.1/16982 |
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