The SCALE DRAM subsystem
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.
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| Format: | Thesis |
| Language: | eng |
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Massachusetts Institute of Technology
2005
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| Online Access: | http://hdl.handle.net/1721.1/17969 |
| _version_ | 1826197642538909696 |
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| author | Pharris, Brian S. (Brian Scott), 1978- |
| author2 | Krste AsanoviÄ. |
| author_facet | Krste AsanoviÄ. Pharris, Brian S. (Brian Scott), 1978- |
| author_sort | Pharris, Brian S. (Brian Scott), 1978- |
| collection | MIT |
| description | Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004. |
| first_indexed | 2024-09-23T10:50:46Z |
| format | Thesis |
| id | mit-1721.1/17969 |
| institution | Massachusetts Institute of Technology |
| language | eng |
| last_indexed | 2024-09-23T10:50:46Z |
| publishDate | 2005 |
| publisher | Massachusetts Institute of Technology |
| record_format | dspace |
| spelling | mit-1721.1/179692019-04-12T15:56:24Z The SCALE DRAM subsystem SCALE memory subsystem Pharris, Brian S. (Brian Scott), 1978- Krste AsanoviÄ. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Electrical Engineering and Computer Science. Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004. Includes bibliographical references (leaf 79). Dynamic Random Access Memory (DRAM) is consuming an ever-increasing portion of a system's energy budget as advances are made in low-power processors. In order to reduce these energy costs, modern DRAM chips implement low-power operating modes that significantly reduce energy consumption but introduce a performance penalty. This thesis discusses the design and evaluation of an energy-aware DRAM subsystem which leverages the power-saving features of modern DRAM chips while maintaining acceptable system performance. As this subsystem may employ a number of different system policies, the effect of each of these policies on system energy and performance is evaluated. The optimal overall policy configurations in terms of energy, delay, and energy-delay product are presented and evaluated. The configuration which minimizes the energy-delay product demonstrates average energy savings of 41.8% as compared to the high-performance configuration, while only introducing an 8.8% performance degradation. by Brian S. Pharris. M.Eng. 2005-06-02T19:27:14Z 2005-06-02T19:27:14Z 2004 2004 Thesis http://hdl.handle.net/1721.1/17969 57174320 eng M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 79 leaves 4258843 bytes 4267345 bytes application/pdf application/pdf application/pdf Massachusetts Institute of Technology |
| spellingShingle | Electrical Engineering and Computer Science. Pharris, Brian S. (Brian Scott), 1978- The SCALE DRAM subsystem |
| title | The SCALE DRAM subsystem |
| title_full | The SCALE DRAM subsystem |
| title_fullStr | The SCALE DRAM subsystem |
| title_full_unstemmed | The SCALE DRAM subsystem |
| title_short | The SCALE DRAM subsystem |
| title_sort | scale dram subsystem |
| topic | Electrical Engineering and Computer Science. |
| url | http://hdl.handle.net/1721.1/17969 |
| work_keys_str_mv | AT pharrisbriansbrianscott1978 thescaledramsubsystem AT pharrisbriansbrianscott1978 scalememorysubsystem AT pharrisbriansbrianscott1978 scaledramsubsystem |