Cell-based array for deep sub-micron technologies
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2003.
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| Format: | Thesis |
| Language: | eng |
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Massachusetts Institute of Technology
2005
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| Online Access: | http://hdl.handle.net/1721.1/18030 |
| _version_ | 1826199819731861504 |
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| author | Oey, James Boe-Kian, 1980- |
| author2 | Christopher J. Terman. |
| author_facet | Christopher J. Terman. Oey, James Boe-Kian, 1980- |
| author_sort | Oey, James Boe-Kian, 1980- |
| collection | MIT |
| description | Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2003. |
| first_indexed | 2024-09-23T11:26:16Z |
| format | Thesis |
| id | mit-1721.1/18030 |
| institution | Massachusetts Institute of Technology |
| language | eng |
| last_indexed | 2024-09-23T11:26:16Z |
| publishDate | 2005 |
| publisher | Massachusetts Institute of Technology |
| record_format | dspace |
| spelling | mit-1721.1/180302019-04-11T13:06:54Z Cell-based array for deep sub-micron technologies Oey, James Boe-Kian, 1980- Christopher J. Terman. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Electrical Engineering and Computer Science. Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2003. Includes bibliographical references (p. 161). In this thesis I explore transistor topologies for high density cell-based arrays that allows for dense computation blocks, small memory cells, and strong signal drivers. This involves simulating different circuit types with HSPICE to determine ideal transistor sizes. Using Magic and the results of the HSPICE simulations, I explore transistor topologies with different ratios of nFets to pFets. An analysis on the technology shows important characteristics for digital systems and how they relate to the explored transistor topologies. by James Boe-Kian Oey. M.Eng. 2005-06-02T19:41:55Z 2005-06-02T19:41:55Z 2003 2003 Thesis http://hdl.handle.net/1721.1/18030 57241123 eng M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 161 p. 7729483 bytes 7751552 bytes application/pdf application/pdf application/pdf Massachusetts Institute of Technology |
| spellingShingle | Electrical Engineering and Computer Science. Oey, James Boe-Kian, 1980- Cell-based array for deep sub-micron technologies |
| title | Cell-based array for deep sub-micron technologies |
| title_full | Cell-based array for deep sub-micron technologies |
| title_fullStr | Cell-based array for deep sub-micron technologies |
| title_full_unstemmed | Cell-based array for deep sub-micron technologies |
| title_short | Cell-based array for deep sub-micron technologies |
| title_sort | cell based array for deep sub micron technologies |
| topic | Electrical Engineering and Computer Science. |
| url | http://hdl.handle.net/1721.1/18030 |
| work_keys_str_mv | AT oeyjamesboekian1980 cellbasedarrayfordeepsubmicrontechnologies |