A shared-memory multiprocessor system using the raw tiled architecture
Thesis (M. Eng. and S.B.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.
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| Format: | Thesis |
| Language: | en_US |
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Massachusetts Institute of Technology
2005
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| Online Access: | http://hdl.handle.net/1721.1/28394 |
| _version_ | 1811090708541472768 |
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| author | Jakab, Levente, 1981- |
| author2 | Anant Agarwal. |
| author_facet | Anant Agarwal. Jakab, Levente, 1981- |
| author_sort | Jakab, Levente, 1981- |
| collection | MIT |
| description | Thesis (M. Eng. and S.B.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004. |
| first_indexed | 2024-09-23T14:50:39Z |
| format | Thesis |
| id | mit-1721.1/28394 |
| institution | Massachusetts Institute of Technology |
| language | en_US |
| last_indexed | 2024-09-23T14:50:39Z |
| publishDate | 2005 |
| publisher | Massachusetts Institute of Technology |
| record_format | dspace |
| spelling | mit-1721.1/283942019-04-11T14:38:01Z A shared-memory multiprocessor system using the raw tiled architecture Jakab, Levente, 1981- Anant Agarwal. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Electrical Engineering and Computer Science. Thesis (M. Eng. and S.B.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004. Includes bibliographical references (p. 203-208). Recent trends in microprocessor design have moved away from dedicated hardware mechanisms to exposed architectures in which basic functionality is implemented in software. To demonstrate the flexibility of this scheme, I implement a shared memory system on Raw, a tiled multiprocessor. A traditional directory-based cache coherence system is used. The directories are fully resident on several tiles, and the remaining tiles act as users, with cache maintenance routines accessed via interrupt. Previous implementations of shared-memory systems have mostly relied on a combination of dedicated hardware and user-enabled software hooks, with one notable exception, Alewife, combining basic hardware with software support for corner cases. Here, the focus is moved to placing as much support for basic cases into software as possible. The system is designed to minimise custom hardware and user responsibilities. I prove the feasibility of such a design on an exposed architecture such as Raw. by Levente Jakab. M.Eng.and S.B. 2005-09-26T20:12:53Z 2005-09-26T20:12:53Z 2004 2004 Thesis http://hdl.handle.net/1721.1/28394 56978495 en_US M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 208 p. 9811968 bytes 9841236 bytes application/pdf application/pdf application/pdf Massachusetts Institute of Technology |
| spellingShingle | Electrical Engineering and Computer Science. Jakab, Levente, 1981- A shared-memory multiprocessor system using the raw tiled architecture |
| title | A shared-memory multiprocessor system using the raw tiled architecture |
| title_full | A shared-memory multiprocessor system using the raw tiled architecture |
| title_fullStr | A shared-memory multiprocessor system using the raw tiled architecture |
| title_full_unstemmed | A shared-memory multiprocessor system using the raw tiled architecture |
| title_short | A shared-memory multiprocessor system using the raw tiled architecture |
| title_sort | shared memory multiprocessor system using the raw tiled architecture |
| topic | Electrical Engineering and Computer Science. |
| url | http://hdl.handle.net/1721.1/28394 |
| work_keys_str_mv | AT jakablevente1981 asharedmemorymultiprocessorsystemusingtherawtiledarchitecture AT jakablevente1981 sharedmemorymultiprocessorsystemusingtherawtiledarchitecture |