Hardware implementation of the Advanced Encryption Standard
Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2003.
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| Format: | Thesis |
| Language: | eng |
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Massachusetts Institute of Technology
2006
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| Online Access: | http://hdl.handle.net/1721.1/29732 |
| _version_ | 1826202034674597888 |
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| author | Maurer, Jennifer (Jennifer Robin), 1979- |
| author2 | Jonathan H. Raymond and Donald E. Troxel. |
| author_facet | Jonathan H. Raymond and Donald E. Troxel. Maurer, Jennifer (Jennifer Robin), 1979- |
| author_sort | Maurer, Jennifer (Jennifer Robin), 1979- |
| collection | MIT |
| description | Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2003. |
| first_indexed | 2024-09-23T12:00:46Z |
| format | Thesis |
| id | mit-1721.1/29732 |
| institution | Massachusetts Institute of Technology |
| language | eng |
| last_indexed | 2024-09-23T12:00:46Z |
| publishDate | 2006 |
| publisher | Massachusetts Institute of Technology |
| record_format | dspace |
| spelling | mit-1721.1/297322019-04-12T23:06:14Z Hardware implementation of the Advanced Encryption Standard Hardware implementation of the AES Maurer, Jennifer (Jennifer Robin), 1979- Jonathan H. Raymond and Donald E. Troxel. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Electrical Engineering and Computer Science. Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2003. Includes bibliographical references (leaves 97-98). This project implements a hardware solution to the Advanced Encryption Standard (AES) algorithm and interfaces to IBM's CoreConnect Bus Architecture. The project is IBM SoftCore compliant, is synthesized to the .18 micron CMOS double-well technology, runs at 133 MHz, and is approximately 706K for the 16x128 bit buffer implementation and 874K gates for the 32x128 bit buffer implementation. Data can be encrypted and decrypted at a throughput of 1Gbps. The work described in the paper was completed as a part of MIT's VI-A program in the ASIC Digital Cores III group of the Microelectronics Division at IBM. by Jennifer Maurer. M.Eng. 2006-03-24T16:20:19Z 2006-03-24T16:20:19Z 2003 2003 Thesis http://hdl.handle.net/1721.1/29732 54040069 eng M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 98 leaves 3092988 bytes 3092797 bytes application/pdf application/pdf application/pdf Massachusetts Institute of Technology |
| spellingShingle | Electrical Engineering and Computer Science. Maurer, Jennifer (Jennifer Robin), 1979- Hardware implementation of the Advanced Encryption Standard |
| title | Hardware implementation of the Advanced Encryption Standard |
| title_full | Hardware implementation of the Advanced Encryption Standard |
| title_fullStr | Hardware implementation of the Advanced Encryption Standard |
| title_full_unstemmed | Hardware implementation of the Advanced Encryption Standard |
| title_short | Hardware implementation of the Advanced Encryption Standard |
| title_sort | hardware implementation of the advanced encryption standard |
| topic | Electrical Engineering and Computer Science. |
| url | http://hdl.handle.net/1721.1/29732 |
| work_keys_str_mv | AT maurerjenniferjenniferrobin1979 hardwareimplementationoftheadvancedencryptionstandard AT maurerjenniferjenniferrobin1979 hardwareimplementationoftheaes |