A model for analysis of the effects of redundancy and error correction on DRAM memory yield and reliability
Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2000.
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| Format: | Thesis |
| Language: | eng |
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Massachusetts Institute of Technology
2006
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| Online Access: | http://hdl.handle.net/1721.1/32094 |
| _version_ | 1826190142500503552 |
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| author | Croswell, Joseph Adam, 1977- |
| author2 | Srinivas Devadas. |
| author_facet | Srinivas Devadas. Croswell, Joseph Adam, 1977- |
| author_sort | Croswell, Joseph Adam, 1977- |
| collection | MIT |
| description | Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2000. |
| first_indexed | 2024-09-23T08:35:41Z |
| format | Thesis |
| id | mit-1721.1/32094 |
| institution | Massachusetts Institute of Technology |
| language | eng |
| last_indexed | 2024-09-23T08:35:41Z |
| publishDate | 2006 |
| publisher | Massachusetts Institute of Technology |
| record_format | dspace |
| spelling | mit-1721.1/320942019-04-09T18:39:30Z A model for analysis of the effects of redundancy and error correction on DRAM memory yield and reliability Croswell, Joseph Adam, 1977- Srinivas Devadas. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Electrical Engineering and Computer Science. Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2000. This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections. Includes bibliographical references (leaf 57). Manufacturing a DRAM module that is error free is a very difficult process. This process is becoming more difficult when only utilizing the current methods for producing an error free DRAM. Error correction codes (ECCs) and cell replacement are two methods currently used in isolation of each other in order to solve two of the problems with this manufacturing process: increasing reliability and increasing yield, respectively. Possible solutions to this problem are proposed and evaluated qualitatively in discussion. Also, a simulation model is produced in order to simulate the impacts of various strategies in order to evaluate their effectiveness. by Joseph Adam Croswell. M.Eng. 2006-03-28T19:50:54Z 2006-03-28T19:50:54Z 2000 2000 Thesis http://hdl.handle.net/1721.1/32094 48981811 eng M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 57 leaves 250474 bytes 249930 bytes application/pdf application/pdf application/pdf Massachusetts Institute of Technology |
| spellingShingle | Electrical Engineering and Computer Science. Croswell, Joseph Adam, 1977- A model for analysis of the effects of redundancy and error correction on DRAM memory yield and reliability |
| title | A model for analysis of the effects of redundancy and error correction on DRAM memory yield and reliability |
| title_full | A model for analysis of the effects of redundancy and error correction on DRAM memory yield and reliability |
| title_fullStr | A model for analysis of the effects of redundancy and error correction on DRAM memory yield and reliability |
| title_full_unstemmed | A model for analysis of the effects of redundancy and error correction on DRAM memory yield and reliability |
| title_short | A model for analysis of the effects of redundancy and error correction on DRAM memory yield and reliability |
| title_sort | model for analysis of the effects of redundancy and error correction on dram memory yield and reliability |
| topic | Electrical Engineering and Computer Science. |
| url | http://hdl.handle.net/1721.1/32094 |
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