Performance, scalability, and flexibility in the RAW network router
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.
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| Format: | Thesis |
| Language: | eng |
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Massachusetts Institute of Technology
2006
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| Online Access: | http://hdl.handle.net/1721.1/33127 |
| _version_ | 1811072940779765760 |
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| author | DeGangi, Anthony M |
| author2 | Umar Saif. |
| author_facet | Umar Saif. DeGangi, Anthony M |
| author_sort | DeGangi, Anthony M |
| collection | MIT |
| description | Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004. |
| first_indexed | 2024-09-23T09:23:10Z |
| format | Thesis |
| id | mit-1721.1/33127 |
| institution | Massachusetts Institute of Technology |
| language | eng |
| last_indexed | 2024-09-23T09:23:10Z |
| publishDate | 2006 |
| publisher | Massachusetts Institute of Technology |
| record_format | dspace |
| spelling | mit-1721.1/331272019-04-10T11:38:20Z Performance, scalability, and flexibility in the RAW network router DeGangi, Anthony M Umar Saif. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Electrical Engineering and Computer Science. Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004. Includes bibliographical references (p. 46). Conventional high speed Internet routers are built using custom designed microprocessors, dubbed network processors, to efficiently handle the task of packet routing. While capable of meeting the performance demanded of them, these custom network processors generally lack the flexibility to incorporate new features and do not scale well beyond that for which they were designed. Furthermore, they tend to suffer from long and costly development cycles, since each new generation must be redesigned to support new features and fabricated anew in hardware. This thesis presents a new design for a network processor, one implemented entirely in software, on a tiled, general purpose microprocessor. The network processor is implemented on the Raw microprocessor, a general purpose microchip developed by the Computer Architecture Group at MIT. The Raw chip consists of sixteen identical processing tiles arranged in a four by four matrix and connected by four inter-tile communication networks; the Raw chip is designed to be able to scale up merely by adding more tiles to the matrix. By taking advantage of the parallelism inherent in the task of packet forwarding on this inherently parallel microprocessor, the Raw network processor is able to achieve performance that matches or exceeds that of commercially available custom designed network processors. At the same time, it maintains the flexibility to incorporate new features since it is implemented entirely in software, as well as the scalability to handle more ports by simply adding more tiles to the microprocessor. by Anthony M. DeGangi. M.Eng. 2006-06-19T17:43:44Z 2006-06-19T17:43:44Z 2004 2004 Thesis http://hdl.handle.net/1721.1/33127 62241139 eng M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 46 p. 2223111 bytes 2223448 bytes application/pdf application/pdf application/pdf Massachusetts Institute of Technology |
| spellingShingle | Electrical Engineering and Computer Science. DeGangi, Anthony M Performance, scalability, and flexibility in the RAW network router |
| title | Performance, scalability, and flexibility in the RAW network router |
| title_full | Performance, scalability, and flexibility in the RAW network router |
| title_fullStr | Performance, scalability, and flexibility in the RAW network router |
| title_full_unstemmed | Performance, scalability, and flexibility in the RAW network router |
| title_short | Performance, scalability, and flexibility in the RAW network router |
| title_sort | performance scalability and flexibility in the raw network router |
| topic | Electrical Engineering and Computer Science. |
| url | http://hdl.handle.net/1721.1/33127 |
| work_keys_str_mv | AT degangianthonym performancescalabilityandflexibilityintherawnetworkrouter |