Software orchestration of instruction level parallelism on tiled processor architectures
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.
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| Format: | Thesis |
| Language: | eng |
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Massachusetts Institute of Technology
2006
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| Online Access: | http://hdl.handle.net/1721.1/33862 |
| _version_ | 1811089623312498688 |
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| author | Lee, Walter (Walter Cheng-Wan) |
| author2 | Anant Agarwal and Saman Amarasinghe. |
| author_facet | Anant Agarwal and Saman Amarasinghe. Lee, Walter (Walter Cheng-Wan) |
| author_sort | Lee, Walter (Walter Cheng-Wan) |
| collection | MIT |
| description | Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005. |
| first_indexed | 2024-09-23T14:22:08Z |
| format | Thesis |
| id | mit-1721.1/33862 |
| institution | Massachusetts Institute of Technology |
| language | eng |
| last_indexed | 2024-09-23T14:22:08Z |
| publishDate | 2006 |
| publisher | Massachusetts Institute of Technology |
| record_format | dspace |
| spelling | mit-1721.1/338622019-04-12T08:51:45Z Software orchestration of instruction level parallelism on tiled processor architectures Software orchestration of ILP on TPAs Lee, Walter (Walter Cheng-Wan) Anant Agarwal and Saman Amarasinghe. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Electrical Engineering and Computer Science. Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005. Includes bibliographical references (p. 135-138). Projection from silicon technology is that while transistor budget will continue to blossom according to Moore's law, latency from global wires will severely limit the ability to scale centralized structures at high frequencies. A tiled processor architecture (TPA) eliminates long wires from its design by distributing its resources over a pipelined interconnect. By exposing the spatial distribution of these resources to the compiler, a TPA allows the compiler to optimize for locality, thus minimizing the distance that data needs to travel to reach the consuming computation. This thesis examines the compiler problem of exploiting instruction level parallelism (ILP) on a TPA. It describes Rawcc, an ILP compiler for Raw, a fully distributed TPA. The thesis examines the implication of the resource distribution on the exploitation of ILP for each of the following resources: instructions, registers, control, data memory, and wires. It designs novel solutions for each one, and it describes the solutions within the integrated framework of a working compiler. Performance is evaluated on a cycle-accurate Raw simulator as well as on a 16-tile Raw chip. Results show that Rawcc can attain modest speedups for fine-grained applications, as well speedups that scale up to 64 tiles for applications with such parallelism. by Walter Lee. Ph.D. 2006-08-25T18:52:01Z 2006-08-25T18:52:01Z 2005 2005 Thesis http://hdl.handle.net/1721.1/33862 66280771 eng M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 138 p. 7423620 bytes 7429379 bytes application/pdf application/pdf application/pdf Massachusetts Institute of Technology |
| spellingShingle | Electrical Engineering and Computer Science. Lee, Walter (Walter Cheng-Wan) Software orchestration of instruction level parallelism on tiled processor architectures |
| title | Software orchestration of instruction level parallelism on tiled processor architectures |
| title_full | Software orchestration of instruction level parallelism on tiled processor architectures |
| title_fullStr | Software orchestration of instruction level parallelism on tiled processor architectures |
| title_full_unstemmed | Software orchestration of instruction level parallelism on tiled processor architectures |
| title_short | Software orchestration of instruction level parallelism on tiled processor architectures |
| title_sort | software orchestration of instruction level parallelism on tiled processor architectures |
| topic | Electrical Engineering and Computer Science. |
| url | http://hdl.handle.net/1721.1/33862 |
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