Software orchestration of instruction level parallelism on tiled processor architectures

Software orchestration of instruction level parallelism on tiled processor architectures

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.

Bibliographic Details
Main Author: Lee, Walter (Walter Cheng-Wan)
Other Authors: Anant Agarwal and Saman Amarasinghe.
Format: Thesis
Language:eng
Published: Massachusetts Institute of Technology 2006
Subjects:
Electrical Engineering and Computer Science.
Online Access:http://hdl.handle.net/1721.1/33862

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