A VLSI systolic array processor for complex singular value decomposition
Thesis (B.S. and M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1994.
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| Format: | Thesis |
| Language: | eng |
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Massachusetts Institute of Technology
2006
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| Online Access: | http://hdl.handle.net/1721.1/34099 |
| _version_ | 1811069178423017472 |
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| author | Niessen, Christopher Charles |
| author2 | Srinivas Devadas and Steven R. Broadstone. |
| author_facet | Srinivas Devadas and Steven R. Broadstone. Niessen, Christopher Charles |
| author_sort | Niessen, Christopher Charles |
| collection | MIT |
| description | Thesis (B.S. and M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1994. |
| first_indexed | 2024-09-23T08:06:57Z |
| format | Thesis |
| id | mit-1721.1/34099 |
| institution | Massachusetts Institute of Technology |
| language | eng |
| last_indexed | 2024-09-23T08:06:57Z |
| publishDate | 2006 |
| publisher | Massachusetts Institute of Technology |
| record_format | dspace |
| spelling | mit-1721.1/340992019-04-09T16:44:42Z A VLSI systolic array processor for complex singular value decomposition Very large scale integration systolic array processor for complex singular value decomposition Niessen, Christopher Charles Srinivas Devadas and Steven R. Broadstone. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Electrical Engineering and Computer Science. Thesis (B.S. and M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1994. Includes bibliographical references (leaves 219-221). The singular value decomposition is one example of a variety of more complex routines that are finding use in modern high performance signal processing systems. In the interest of achieving the maximum possible performance, a systolic array processor for computing the singular value decomposition of an arbitrary complex matrix was designed using a silicon compiler system. This system allows for ease of design by specification of the processor architecture in a high level language, utilizing parts from a variety of cell libraries, while still benefiting from the power of custom VLSI. The level of abstraction provided by this system allowed more complex functional units to be built up from existing simple library parts. A novel fast interpolation cell for computation of square roots and inverse square roots was designed, allowing for a new algebraic approach to the singular value decomposition problem. The processors connect together in a systolic array to maximize computational efficiency while minimizing overhead due to high communication requirements. by Christopher Charles Niessen. B.S.and M.S. 2006-09-28T15:02:33Z 2006-09-28T15:02:33Z 1994 1994 Thesis http://hdl.handle.net/1721.1/34099 46973227 eng M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 221 leaves 8569735 bytes 8579075 bytes application/pdf application/pdf application/pdf Massachusetts Institute of Technology |
| spellingShingle | Electrical Engineering and Computer Science. Niessen, Christopher Charles A VLSI systolic array processor for complex singular value decomposition |
| title | A VLSI systolic array processor for complex singular value decomposition |
| title_full | A VLSI systolic array processor for complex singular value decomposition |
| title_fullStr | A VLSI systolic array processor for complex singular value decomposition |
| title_full_unstemmed | A VLSI systolic array processor for complex singular value decomposition |
| title_short | A VLSI systolic array processor for complex singular value decomposition |
| title_sort | vlsi systolic array processor for complex singular value decomposition |
| topic | Electrical Engineering and Computer Science. |
| url | http://hdl.handle.net/1721.1/34099 |
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