Scale Control Processor Test-Chip

We are investigating vector-thread architectures which provide competitive performance and efficiency across a broad class of application domains. Vector-thread architectures unify data-level, thread-level, and instruction-level parallelism, providing new ways of parallelizing codes that are difficu...

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Bibliographic Details
Main Authors: Batten, Christopher, Krashinsky, Ronny, Asanovic, Krste
Other Authors: Krste Asanovic
Language:en_US
Published: 2007
Online Access:http://hdl.handle.net/1721.1/35724