Sánchez, C., & Devadas, S. (2007). BIST test pattern generator based on partitioning circuit inputs. Massachusetts Institute of Technology.
Chicago Style (17th ed.) CitationSánchez, Clara, and Srinivas Devadas. BIST Test Pattern Generator Based on Partitioning Circuit Inputs. Massachusetts Institute of Technology, 2007.
MLA (9th ed.) CitationSánchez, Clara, and Srinivas Devadas. BIST Test Pattern Generator Based on Partitioning Circuit Inputs. Massachusetts Institute of Technology, 2007.
Warning: These citations may not always be 100% accurate.