BIST test pattern generator based on partitioning circuit inputs
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1995.
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| Format: | Thesis |
| Language: | eng |
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Massachusetts Institute of Technology
2007
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| Online Access: | http://hdl.handle.net/1721.1/36580 |
| _version_ | 1826198134591586304 |
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| author | Sánchez, Clara |
| author2 | Srinivas Devadas. |
| author_facet | Srinivas Devadas. Sánchez, Clara |
| author_sort | Sánchez, Clara |
| collection | MIT |
| description | Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1995. |
| first_indexed | 2024-09-23T10:59:33Z |
| format | Thesis |
| id | mit-1721.1/36580 |
| institution | Massachusetts Institute of Technology |
| language | eng |
| last_indexed | 2024-09-23T10:59:33Z |
| publishDate | 2007 |
| publisher | Massachusetts Institute of Technology |
| record_format | dspace |
| spelling | mit-1721.1/365802019-04-11T05:54:40Z BIST test pattern generator based on partitioning circuit inputs Sánchez, Clara Srinivas Devadas. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science Electrical Engineering and Computer Science Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1995. Includes bibliographical references (leaves 33-35). by Clara Sánchez. M.Eng. 2007-03-12T17:33:35Z 2007-03-12T17:33:35Z 1995 1995 Thesis http://hdl.handle.net/1721.1/36580 33343502 eng M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 35 leaves application/pdf Massachusetts Institute of Technology |
| spellingShingle | Electrical Engineering and Computer Science Sánchez, Clara BIST test pattern generator based on partitioning circuit inputs |
| title | BIST test pattern generator based on partitioning circuit inputs |
| title_full | BIST test pattern generator based on partitioning circuit inputs |
| title_fullStr | BIST test pattern generator based on partitioning circuit inputs |
| title_full_unstemmed | BIST test pattern generator based on partitioning circuit inputs |
| title_short | BIST test pattern generator based on partitioning circuit inputs |
| title_sort | bist test pattern generator based on partitioning circuit inputs |
| topic | Electrical Engineering and Computer Science |
| url | http://hdl.handle.net/1721.1/36580 |
| work_keys_str_mv | AT sanchezclara bisttestpatterngeneratorbasedonpartitioningcircuitinputs |