Automating the construction of a complier heuristics using machine learning
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006.
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| Format: | Thesis |
| Language: | eng |
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Massachusetts Institute of Technology
2008
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| Online Access: | http://dspace.mit.edu/handle/1721.1/37902 http://hdl.handle.net/1721.1/37902 |
| _version_ | 1826192522270998528 |
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| author | Stephenson, Mark William, 1975- |
| author2 | Saman Amarasinghe. |
| author_facet | Saman Amarasinghe. Stephenson, Mark William, 1975- |
| author_sort | Stephenson, Mark William, 1975- |
| collection | MIT |
| description | Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006. |
| first_indexed | 2024-09-23T09:18:46Z |
| format | Thesis |
| id | mit-1721.1/37902 |
| institution | Massachusetts Institute of Technology |
| language | eng |
| last_indexed | 2024-09-23T09:18:46Z |
| publishDate | 2008 |
| publisher | Massachusetts Institute of Technology |
| record_format | dspace |
| spelling | mit-1721.1/379022019-04-11T04:31:53Z Automating the construction of a complier heuristics using machine learning Stephenson, Mark William, 1975- Saman Amarasinghe. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Electrical Engineering and Computer Science. Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006. Includes bibliographical references (p. 153-162). Compiler writers are expected to create effective and inexpensive solutions to NP-hard problems such as instruction scheduling and register allocation. To make matters worse, separate optimization phases have strong interactions and competing resource constraints. Compiler writers deal with system complexity by dividing the problem into multiple phases and devising approximate heuristics for each phase. However, to achieve satisfactory performance, developers are forced to manually tweak their heuristics with trial-and-error experimentation. In this dissertation I present meta optimization, a methodology for automatically constructing high quality compiler heuristics using machine learning techniques. This thesis describes machine-learned heuristics for three important compiler optimizations: hyperblock formation, register allocation, and loop unrolling. The machine-learned heuristics outperform (by as much as 3x in some cases) their state-of-the-art hand-crafted counterparts. By automatically collecting data and systematically analyzing them, my techniques discover subtle interactions that even experienced engineers would likely overlook. In addition to improving performance, my techniques can significantly reduce the human effort involved in compiler design. (cont.) Machine learning algorithms can design critical portions of compiler heuristics, thereby freeing the human designer to focus on compiler correctness. The progression of experiments I conduct in this thesis leads to collaborative compilation, an approach which enables ordinary users to transparently train compiler heuristics by running their applications as they normally would. The collaborative system automatically adapts itself to the applications in which a community of users is interested. by Mark W. Stephenson. Ph.D. 2008-02-28T15:42:30Z 2008-02-28T15:42:30Z 2006 2006 Thesis http://dspace.mit.edu/handle/1721.1/37902 http://hdl.handle.net/1721.1/37902 132792993 eng M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/37902 http://dspace.mit.edu/handle/1721.1/7582 162 p. application/pdf Massachusetts Institute of Technology |
| spellingShingle | Electrical Engineering and Computer Science. Stephenson, Mark William, 1975- Automating the construction of a complier heuristics using machine learning |
| title | Automating the construction of a complier heuristics using machine learning |
| title_full | Automating the construction of a complier heuristics using machine learning |
| title_fullStr | Automating the construction of a complier heuristics using machine learning |
| title_full_unstemmed | Automating the construction of a complier heuristics using machine learning |
| title_short | Automating the construction of a complier heuristics using machine learning |
| title_sort | automating the construction of a complier heuristics using machine learning |
| topic | Electrical Engineering and Computer Science. |
| url | http://dspace.mit.edu/handle/1721.1/37902 http://hdl.handle.net/1721.1/37902 |
| work_keys_str_mv | AT stephensonmarkwilliam1975 automatingtheconstructionofacomplierheuristicsusingmachinelearning |