Circuits for high-performance low-power VLSI logic
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006.
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| Format: | Thesis |
| Language: | eng |
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Massachusetts Institute of Technology
2007
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| Online Access: | http://hdl.handle.net/1721.1/37906 |
| _version_ | 1826189789309698048 |
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| author | Ma, Albert |
| author2 | Krste Asanović. |
| author_facet | Krste Asanović. Ma, Albert |
| author_sort | Ma, Albert |
| collection | MIT |
| description | Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006. |
| first_indexed | 2024-09-23T08:21:54Z |
| format | Thesis |
| id | mit-1721.1/37906 |
| institution | Massachusetts Institute of Technology |
| language | eng |
| last_indexed | 2024-09-23T08:21:54Z |
| publishDate | 2007 |
| publisher | Massachusetts Institute of Technology |
| record_format | dspace |
| spelling | mit-1721.1/379062019-04-09T18:06:51Z Circuits for high-performance low-power VLSI logic Circuits for high-performance low-power very large scale integration of circuits logic Ma, Albert Krste Asanović. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Electrical Engineering and Computer Science. Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006. Includes bibliographical references (p. 85-88). The demands of future computing, as well as the challenges of nanometer-era VLSI design, require new digital logic techniques and styles that are simultaneously high performance, energy efficient, and robust to noise and variation. We propose a new family of logic styles called Preset Skewed Static Logic (PSSL). PSSL bridges the gap between the two main logic styles, static CMOS logic and domino logic, occupying an intermediate region in the energy-delay-robustness space between the two. PSSL is better than domino in terms of energy and robustness, and is better than static CMOS in terms of delay. PSSL works by partially overlapping the execution of consecutive iterations through speculative evaluation. This is accomplished by presetting nodes at register boundaries before input arrival. by Albert Ma. Ph.D. 2007-07-18T13:07:52Z 2007-07-18T13:07:52Z 2006 2006 Thesis http://hdl.handle.net/1721.1/37906 133104456 eng M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 88 p. application/pdf Massachusetts Institute of Technology |
| spellingShingle | Electrical Engineering and Computer Science. Ma, Albert Circuits for high-performance low-power VLSI logic |
| title | Circuits for high-performance low-power VLSI logic |
| title_full | Circuits for high-performance low-power VLSI logic |
| title_fullStr | Circuits for high-performance low-power VLSI logic |
| title_full_unstemmed | Circuits for high-performance low-power VLSI logic |
| title_short | Circuits for high-performance low-power VLSI logic |
| title_sort | circuits for high performance low power vlsi logic |
| topic | Electrical Engineering and Computer Science. |
| url | http://hdl.handle.net/1721.1/37906 |
| work_keys_str_mv | AT maalbert circuitsforhighperformancelowpowervlsilogic AT maalbert circuitsforhighperformancelowpowerverylargescaleintegrationofcircuitslogic |