Summarizing multiprocessor program execution with versatile, microarchitecture-independent snapshots
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006.
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| Format: | Thesis |
| Language: | eng |
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Massachusetts Institute of Technology
2007
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| Online Access: | http://hdl.handle.net/1721.1/38224 |
| _version_ | 1811087548821274624 |
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| author | Barr, Kenneth C. (Kenneth Charles), 1978- |
| author2 | Krste Asanović. |
| author_facet | Krste Asanović. Barr, Kenneth C. (Kenneth Charles), 1978- |
| author_sort | Barr, Kenneth C. (Kenneth Charles), 1978- |
| collection | MIT |
| description | Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006. |
| first_indexed | 2024-09-23T13:47:52Z |
| format | Thesis |
| id | mit-1721.1/38224 |
| institution | Massachusetts Institute of Technology |
| language | eng |
| last_indexed | 2024-09-23T13:47:52Z |
| publishDate | 2007 |
| publisher | Massachusetts Institute of Technology |
| record_format | dspace |
| spelling | mit-1721.1/382242019-04-12T08:53:03Z Summarizing multiprocessor program execution with versatile, microarchitecture-independent snapshots Barr, Kenneth C. (Kenneth Charles), 1978- Krste Asanović. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Electrical Engineering and Computer Science. Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006. Includes bibliographical references (p. 131-137). Computer architects rely heavily on software simulation to evaluate, refine, and validate new designs before they are implemented. However, simulation time continues to increase as computers become more complex and multicore designs become more common. This thesis investigates software structures and algorithms for quickly simulating modern cache-coherent multiprocessors by amortizing the time spent to simulate the memory system and branch predictors. The Memory Timestamp Record (MTR) summarizes the directory and cache state of a multiprocessor system in a compact data structure. A single MTR snapshot is versatile enough to reconstruct the microarchitectural state resulting from various coherence protocols and cache organizations. The MTR may be quickly updated by each simulated processor during a fast-forwarding phase and optionally stored off-line for reuse. To fill large branch prediction tables, we introduce Branch Predictor-based Compression (BPC) which compactly stores a branch trace so that it may be used to fill in any branch predictor structure. An entire BPC trace requires less space than single discrete predictor snapshots, and it may be decompressed 3-6x faster than performing functional simulation. by Kenneth C. Barr. Ph.D. 2007-08-03T15:41:36Z 2007-08-03T15:41:36Z 2006 2006 Thesis http://hdl.handle.net/1721.1/38224 153920635 eng M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 137 p. application/pdf Massachusetts Institute of Technology |
| spellingShingle | Electrical Engineering and Computer Science. Barr, Kenneth C. (Kenneth Charles), 1978- Summarizing multiprocessor program execution with versatile, microarchitecture-independent snapshots |
| title | Summarizing multiprocessor program execution with versatile, microarchitecture-independent snapshots |
| title_full | Summarizing multiprocessor program execution with versatile, microarchitecture-independent snapshots |
| title_fullStr | Summarizing multiprocessor program execution with versatile, microarchitecture-independent snapshots |
| title_full_unstemmed | Summarizing multiprocessor program execution with versatile, microarchitecture-independent snapshots |
| title_short | Summarizing multiprocessor program execution with versatile, microarchitecture-independent snapshots |
| title_sort | summarizing multiprocessor program execution with versatile microarchitecture independent snapshots |
| topic | Electrical Engineering and Computer Science. |
| url | http://hdl.handle.net/1721.1/38224 |
| work_keys_str_mv | AT barrkennethckennethcharles1978 summarizingmultiprocessorprogramexecutionwithversatilemicroarchitectureindependentsnapshots |