A synchronous communication system for a software-based Byzantine fault tolerant computer
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006.
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| Format: | Thesis |
| Language: | eng |
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Massachusetts Institute of Technology
2008
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| Online Access: | http://hdl.handle.net/1721.1/41226 |
| _version_ | 1826208806647889920 |
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| author | Sterling, Reuben Marbell |
| author2 | Roger Racine. |
| author_facet | Roger Racine. Sterling, Reuben Marbell |
| author_sort | Sterling, Reuben Marbell |
| collection | MIT |
| description | Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006. |
| first_indexed | 2024-09-23T14:12:56Z |
| format | Thesis |
| id | mit-1721.1/41226 |
| institution | Massachusetts Institute of Technology |
| language | eng |
| last_indexed | 2024-09-23T14:12:56Z |
| publishDate | 2008 |
| publisher | Massachusetts Institute of Technology |
| record_format | dspace |
| spelling | mit-1721.1/412262019-04-12T16:07:40Z A synchronous communication system for a software-based Byzantine fault tolerant computer Sterling, Reuben Marbell Roger Racine. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Electrical Engineering and Computer Science. Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006. This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections. Includes bibliographical references (p. 155-156). This thesis describes the redesign of a Byzantine-resilient, quad-redundant computer to remove proprietary hardware components. The basic architecture consists of four Commercial Off-The-Shelf (COTS) processors in a completely-connected network of point-to-point ethernet connections. In particular, the focus of this thesis is an algorithm that combines clock synchronization and communications between fault containment regions by inferring relative clock skew from the arrival time of expected messages. Both a failsafe and a fault-tolerant algorithm are discussed, though the fault-tolerant algorithm is not fully analyzed. The performance of a prototype and the failsafe synchronization algorithm are discussed. by Reuben Marbell Sterling. M.Eng. 2008-04-23T12:28:26Z 2008-04-23T12:28:26Z 2006 2006 Thesis http://hdl.handle.net/1721.1/41226 216884403 eng M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 156 p. application/pdf Massachusetts Institute of Technology |
| spellingShingle | Electrical Engineering and Computer Science. Sterling, Reuben Marbell A synchronous communication system for a software-based Byzantine fault tolerant computer |
| title | A synchronous communication system for a software-based Byzantine fault tolerant computer |
| title_full | A synchronous communication system for a software-based Byzantine fault tolerant computer |
| title_fullStr | A synchronous communication system for a software-based Byzantine fault tolerant computer |
| title_full_unstemmed | A synchronous communication system for a software-based Byzantine fault tolerant computer |
| title_short | A synchronous communication system for a software-based Byzantine fault tolerant computer |
| title_sort | synchronous communication system for a software based byzantine fault tolerant computer |
| topic | Electrical Engineering and Computer Science. |
| url | http://hdl.handle.net/1721.1/41226 |
| work_keys_str_mv | AT sterlingreubenmarbell asynchronouscommunicationsystemforasoftwarebasedbyzantinefaulttolerantcomputer AT sterlingreubenmarbell synchronouscommunicationsystemforasoftwarebasedbyzantinefaulttolerantcomputer |