A hierarchical bottom-up, equation-based optimization design methodology
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, June 2007.
| Main Author: | |
|---|---|
| Other Authors: | |
| Format: | Thesis |
| Language: | eng |
| Published: |
Massachusetts Institute of Technology
2008
|
| Subjects: | |
| Online Access: | http://hdl.handle.net/1721.1/41548 |
| _version_ | 1811095039341756416 |
|---|---|
| author | Sanchez, William R |
| author2 | Joel Dawson. |
| author_facet | Joel Dawson. Sanchez, William R |
| author_sort | Sanchez, William R |
| collection | MIT |
| description | Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, June 2007. |
| first_indexed | 2024-09-23T16:09:32Z |
| format | Thesis |
| id | mit-1721.1/41548 |
| institution | Massachusetts Institute of Technology |
| language | eng |
| last_indexed | 2024-09-23T16:09:32Z |
| publishDate | 2008 |
| publisher | Massachusetts Institute of Technology |
| record_format | dspace |
| spelling | mit-1721.1/415482019-04-11T14:24:45Z A hierarchical bottom-up, equation-based optimization design methodology hierarchical bottom-up, equation-based optimization methodology for system-level design Sanchez, William R Joel Dawson. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Electrical Engineering and Computer Science. Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, June 2007. This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections. "May 2007." Includes bibliographical references (p. 79-82). We have implemented a segment of an RF transmitter signal chain in discrete components using bipolar transistors. We formulated both a broadband amplifier and mixer as mathematical programs (MP) and extracted Pareto-optimal (PO) [1-3] tradeoff surfaces. Abstracting these PO surfaces in place of the blocks at the system level, we have demonstrated a new hierarchical system design methodology. Furthermore, the optimization, simulation, and measured results are consistent at all levels of hierarchy. Keywords: System design, optimization, geometric programming, analog circuits, Pareto-optimal. by William R. Sanchez. M.Eng. 2008-05-19T14:59:35Z 2008-05-19T14:59:35Z 2007 Thesis http://hdl.handle.net/1721.1/41548 220924657 eng M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 82 p. application/pdf Massachusetts Institute of Technology |
| spellingShingle | Electrical Engineering and Computer Science. Sanchez, William R A hierarchical bottom-up, equation-based optimization design methodology |
| title | A hierarchical bottom-up, equation-based optimization design methodology |
| title_full | A hierarchical bottom-up, equation-based optimization design methodology |
| title_fullStr | A hierarchical bottom-up, equation-based optimization design methodology |
| title_full_unstemmed | A hierarchical bottom-up, equation-based optimization design methodology |
| title_short | A hierarchical bottom-up, equation-based optimization design methodology |
| title_sort | hierarchical bottom up equation based optimization design methodology |
| topic | Electrical Engineering and Computer Science. |
| url | http://hdl.handle.net/1721.1/41548 |
| work_keys_str_mv | AT sanchezwilliamr ahierarchicalbottomupequationbasedoptimizationdesignmethodology AT sanchezwilliamr hierarchicalbottomupequationbasedoptimizationmethodologyforsystemleveldesign AT sanchezwilliamr hierarchicalbottomupequationbasedoptimizationdesignmethodology |