Variation-aware placement tool for Field Programmable Gate Array devices

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2007.

Bibliographic Details
Main Author: Perez, Christopher E
Other Authors: Arif Rahman and Charles G. Sodini.
Format: Thesis
Language:eng
Published: Massachusetts Institute of Technology 2008
Subjects:
Online Access:http://hdl.handle.net/1721.1/41664
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author Perez, Christopher E
author2 Arif Rahman and Charles G. Sodini.
author_facet Arif Rahman and Charles G. Sodini.
Perez, Christopher E
author_sort Perez, Christopher E
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description Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2007.
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spelling mit-1721.1/416642019-04-10T15:26:14Z Variation-aware placement tool for Field Programmable Gate Array devices process variation-aware placement tool for FGPA devices Perez, Christopher E Arif Rahman and Charles G. Sodini. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Electrical Engineering and Computer Science. Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2007. Includes bibliographical references (p. 97-98). Introduction: As semiconductor technologies become more advanced, process variations within microelectronic devices, including variations in channel length or in oxide thickness, play a much more important role with regards to circuit delay and leakage power dissipation. These process variations cause variability in circuit performance characteristics that can be minimized by improving process control techniques, resulting in more predictable behavior. However, if we are concerned with programmable logic devices like FPGAs affected by variation, the circuit designer in the field has no control over or knowledge about the manner in which process variations affect the device and the final circuit implementation. Our research here is aimed at developing and incorporating process variation models into circuit design and implementation tools for FPGAs. With variation aware tools, programmable logic device users will have the opportunity to produce circuit implementations that are fully optimized for performance given the presence of process variations. by Christopher E. Perez. M.Eng. 2008-05-19T16:06:46Z 2008-05-19T16:06:46Z 2007 2007 Thesis http://hdl.handle.net/1721.1/41664 220913621 eng M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 98 p. application/pdf Massachusetts Institute of Technology
spellingShingle Electrical Engineering and Computer Science.
Perez, Christopher E
Variation-aware placement tool for Field Programmable Gate Array devices
title Variation-aware placement tool for Field Programmable Gate Array devices
title_full Variation-aware placement tool for Field Programmable Gate Array devices
title_fullStr Variation-aware placement tool for Field Programmable Gate Array devices
title_full_unstemmed Variation-aware placement tool for Field Programmable Gate Array devices
title_short Variation-aware placement tool for Field Programmable Gate Array devices
title_sort variation aware placement tool for field programmable gate array devices
topic Electrical Engineering and Computer Science.
url http://hdl.handle.net/1721.1/41664
work_keys_str_mv AT perezchristophere variationawareplacementtoolforfieldprogrammablegatearraydevices
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