Flexible MIPS Soft Processor Architecture
The flexible MIPS soft processor architecture borrows selected technologies from high-performance computing to deliver a modular, highly customizable CPU targeted towards FPGA implementations for embedded systems; the objective is to provide a more flexible architectural alternative to coprocessor-b...
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2008
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| Online Access: | http://hdl.handle.net/1721.1/41874 |
| _version_ | 1826197354619863040 |
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| author | Carli, Roberto |
| author2 | Chris Terman |
| author_facet | Chris Terman Carli, Roberto |
| author_sort | Carli, Roberto |
| collection | MIT |
| description | The flexible MIPS soft processor architecture borrows selected technologies from high-performance computing to deliver a modular, highly customizable CPU targeted towards FPGA implementations for embedded systems; the objective is to provide a more flexible architectural alternative to coprocessor-based solutions. The processor performs out-of-order execution on parallel functional units, it delivers in-order instruction commit and it is compatible with the MIPS-1 Instruction Set Architecture. Amongst many available options, the user can introduce custom instructions and matching functional units; modify existing units; change the pipelining depth within functional units to any fixed or variable value; customize instruction definitions in terms of operands, control signals and register file interaction; insert multiple redundant functional units for improved performance. The flexibility provided by the architecture allows the user to expand the processor functionality to implement instructions of coprocessor-level complexity through additional functional units. The processor design was implemented and simulated on two FPGA platforms, tested on multiple applications, and compared to three commercially available soft processor solutions in terms of features, area, clock frequency and benchmark performance. |
| first_indexed | 2024-09-23T10:46:25Z |
| id | mit-1721.1/41874 |
| institution | Massachusetts Institute of Technology |
| last_indexed | 2024-09-23T10:46:25Z |
| publishDate | 2008 |
| record_format | dspace |
| spelling | mit-1721.1/418742019-04-11T03:10:12Z Flexible MIPS Soft Processor Architecture Carli, Roberto Chris Terman Computer Architecture The flexible MIPS soft processor architecture borrows selected technologies from high-performance computing to deliver a modular, highly customizable CPU targeted towards FPGA implementations for embedded systems; the objective is to provide a more flexible architectural alternative to coprocessor-based solutions. The processor performs out-of-order execution on parallel functional units, it delivers in-order instruction commit and it is compatible with the MIPS-1 Instruction Set Architecture. Amongst many available options, the user can introduce custom instructions and matching functional units; modify existing units; change the pipelining depth within functional units to any fixed or variable value; customize instruction definitions in terms of operands, control signals and register file interaction; insert multiple redundant functional units for improved performance. The flexibility provided by the architecture allows the user to expand the processor functionality to implement instructions of coprocessor-level complexity through additional functional units. The processor design was implemented and simulated on two FPGA platforms, tested on multiple applications, and compared to three commercially available soft processor solutions in terms of features, area, clock frequency and benchmark performance. 2008-07-02T06:00:36Z 2008-07-02T06:00:36Z 2008-06-16 MIT-CSAIL-TR-2008-036 http://hdl.handle.net/1721.1/41874 Massachusetts Institute of Technology Computer Science and Artificial Intelligence Laboratory 49 p. application/pdf application/postscript |
| spellingShingle | Carli, Roberto Flexible MIPS Soft Processor Architecture |
| title | Flexible MIPS Soft Processor Architecture |
| title_full | Flexible MIPS Soft Processor Architecture |
| title_fullStr | Flexible MIPS Soft Processor Architecture |
| title_full_unstemmed | Flexible MIPS Soft Processor Architecture |
| title_short | Flexible MIPS Soft Processor Architecture |
| title_sort | flexible mips soft processor architecture |
| url | http://hdl.handle.net/1721.1/41874 |
| work_keys_str_mv | AT carliroberto flexiblemipssoftprocessorarchitecture |