(VDL)² : a jitter measurement built-in self-test circuit for phase locked loops
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.
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| Format: | Thesis |
| Language: | eng |
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Massachusetts Institute of Technology
2008
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| Online Access: | http://hdl.handle.net/1721.1/42119 |
| _version_ | 1826192944403578880 |
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| author | Kam, Brandon Ray |
| author2 | Stephen D. Wyatt and Michael H. Perrott. |
| author_facet | Stephen D. Wyatt and Michael H. Perrott. Kam, Brandon Ray |
| author_sort | Kam, Brandon Ray |
| collection | MIT |
| description | Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005. |
| first_indexed | 2024-09-23T09:31:15Z |
| format | Thesis |
| id | mit-1721.1/42119 |
| institution | Massachusetts Institute of Technology |
| language | eng |
| last_indexed | 2024-09-23T09:31:15Z |
| publishDate | 2008 |
| publisher | Massachusetts Institute of Technology |
| record_format | dspace |
| spelling | mit-1721.1/421192019-04-10T08:21:15Z (VDL)² : a jitter measurement built-in self-test circuit for phase locked loops Jitter measurement built-in self-test circuit for phase locked loops Kam, Brandon Ray Stephen D. Wyatt and Michael H. Perrott. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Electrical Engineering and Computer Science. Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005. Includes bibliographical references (p. 77-79). This paper discusses the development of a new type of BIST circuit, the (VDL)2, with the purpose of measuring jitter in IBM's phase locked loops. The (VDL)2, which stands for Variable Vernier Digital Delay Locked Line, implements both cycle-to-cycle and phase jitter measurements, by using a digital delay locked loop and a 60 stage Vernier delay line. This achieves a nominal jitter resolution of 10 ps with a capture range of +/- 150 ps and does so in real time. The proposed application for this circuit is during manufacturing test of the PLL. The circuit is implemented in IBM's 90 nm process and was completed in the PLL and Clocking Development ASIC group at IBM Microelectronics in Essex Junction, Vermont as part of the VI-A program. by Brandon Ray Kam. M.Eng. 2008-09-03T14:38:51Z 2008-09-03T14:38:51Z 2005 2005 Thesis http://hdl.handle.net/1721.1/42119 227033826 eng M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 79 p. application/pdf Massachusetts Institute of Technology |
| spellingShingle | Electrical Engineering and Computer Science. Kam, Brandon Ray (VDL)² : a jitter measurement built-in self-test circuit for phase locked loops |
| title | (VDL)² : a jitter measurement built-in self-test circuit for phase locked loops |
| title_full | (VDL)² : a jitter measurement built-in self-test circuit for phase locked loops |
| title_fullStr | (VDL)² : a jitter measurement built-in self-test circuit for phase locked loops |
| title_full_unstemmed | (VDL)² : a jitter measurement built-in self-test circuit for phase locked loops |
| title_short | (VDL)² : a jitter measurement built-in self-test circuit for phase locked loops |
| title_sort | vdl ² a jitter measurement built in self test circuit for phase locked loops |
| topic | Electrical Engineering and Computer Science. |
| url | http://hdl.handle.net/1721.1/42119 |
| work_keys_str_mv | AT kambrandonray vdl2ajittermeasurementbuiltinselftestcircuitforphaselockedloops AT kambrandonray jittermeasurementbuiltinselftestcircuitforphaselockedloops |