Procedural layout of a high-speed floating-point arithmetic unit

Procedural layout of a high-speed floating-point arithmetic unit

Originally presented as author's thesis (Electrical Engineer --Massachusetts Institute of Technology) 1985.

Bibliographic Details
Other Authors:	Armstrong, Robert Clyde.
Language:	eng
Published:	Massachusetts Institute of Technology, Research Laboratory of Electronics 2004
Subjects:	TK7855.M41 R43 no.508
Online Access:	http://hdl.handle.net/1721.1/4235

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