Emulation of microprocessor memory systems using the RAMP design framework
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.
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| Format: | Thesis |
| Language: | eng |
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Massachusetts Institute of Technology
2008
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| Online Access: | http://hdl.handle.net/1721.1/43033 |
| _version_ | 1811074185523363840 |
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| author | Khan, Asif I. (Asif Imtiaz) |
| author2 | Krste Asanović. |
| author_facet | Krste Asanović. Khan, Asif I. (Asif Imtiaz) |
| author_sort | Khan, Asif I. (Asif Imtiaz) |
| collection | MIT |
| description | Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008. |
| first_indexed | 2024-09-23T09:44:47Z |
| format | Thesis |
| id | mit-1721.1/43033 |
| institution | Massachusetts Institute of Technology |
| language | eng |
| last_indexed | 2024-09-23T09:44:47Z |
| publishDate | 2008 |
| publisher | Massachusetts Institute of Technology |
| record_format | dspace |
| spelling | mit-1721.1/430332019-04-11T12:31:15Z Emulation of microprocessor memory systems using the RAMP design framework Khan, Asif I. (Asif Imtiaz) Krste Asanović. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Electrical Engineering and Computer Science. Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008. Includes bibliographical references (p. 49-50). With the computer hardware industry and the academic world focused on multiprocessor systems, the RAMP project is aiming to provide the infrastructure for supporting high-speed emulation of large scale, massively-parallel multiprocessor systems using FPGAs. The RAMP design framework provides the platform for building this infrastructure. This research utilizes this design framework to emulate various microprocessor memory systems through a model built in an FPGA. We model both the latency and the bandwidth of memory systems through a parameterized emulation platform, thereby, demonstrating the validity of the design framework. We also show the efficiency of the framework through an evaluation of the utilized FPGA resources. by Asif I. Khan. S.M. 2008-11-07T18:54:24Z 2008-11-07T18:54:24Z 2008 2008 Thesis http://hdl.handle.net/1721.1/43033 243608011 eng M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 50 leaves application/pdf Massachusetts Institute of Technology |
| spellingShingle | Electrical Engineering and Computer Science. Khan, Asif I. (Asif Imtiaz) Emulation of microprocessor memory systems using the RAMP design framework |
| title | Emulation of microprocessor memory systems using the RAMP design framework |
| title_full | Emulation of microprocessor memory systems using the RAMP design framework |
| title_fullStr | Emulation of microprocessor memory systems using the RAMP design framework |
| title_full_unstemmed | Emulation of microprocessor memory systems using the RAMP design framework |
| title_short | Emulation of microprocessor memory systems using the RAMP design framework |
| title_sort | emulation of microprocessor memory systems using the ramp design framework |
| topic | Electrical Engineering and Computer Science. |
| url | http://hdl.handle.net/1721.1/43033 |
| work_keys_str_mv | AT khanasifiasifimtiaz emulationofmicroprocessormemorysystemsusingtherampdesignframework |