Channel coding for high speed links
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, February 2008.
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| Format: | Thesis |
| Language: | eng |
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Massachusetts Institute of Technology
2008
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| Online Access: | http://hdl.handle.net/1721.1/43050 |
| _version_ | 1811093054864490496 |
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| author | Blitvic, Natasa |
| author2 | Vladimir Stojanovic. |
| author_facet | Vladimir Stojanovic. Blitvic, Natasa |
| author_sort | Blitvic, Natasa |
| collection | MIT |
| description | Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, February 2008. |
| first_indexed | 2024-09-23T15:38:44Z |
| format | Thesis |
| id | mit-1721.1/43050 |
| institution | Massachusetts Institute of Technology |
| language | eng |
| last_indexed | 2024-09-23T15:38:44Z |
| publishDate | 2008 |
| publisher | Massachusetts Institute of Technology |
| record_format | dspace |
| spelling | mit-1721.1/430502019-04-12T09:47:53Z Channel coding for high speed links Blitvic, Natasa Vladimir Stojanovic. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Electrical Engineering and Computer Science. Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, February 2008. Includes bibliographical references (p. 139-144). This thesis explores the benefit of channel coding for high-speed backplane or chip-to-chip interconnects, referred to as the high-speed links. Although both power-constrained and bandwidth-limited, the high-speed links need to support data rates in the Gbps range at low error probabilities. Modeling the high-speed link as a communication system with noise and intersymbol interference (ISI), this work identifies three operating regimes based on the underlying dominant error mechanisms. The resulting framework is used to identify the conditions under which standard error control codes perform optimally, incur an impractically large overhead, or provide the optimal performance in the form of a single parity check code. For the regime where the standard error control codes are impractical, this thesis introduces low-complexity block codes, termed pattern-eliminating codes (PEC), which achieve a potentially large performance improvement over channels with residual ISI. The codes are systematic, require no decoding and allow for simple encoding. They can also be additionally endowed with a (0, n - 1) run-length-limiting property. The simulation results show that the simplest PEC can provide error-rate reductions of several orders of magnitude, even with rate penalty taken into account. It is also shown that channel conditioning, such as equalization, can have a large effect on the code performance and potentially large gains can be derived from optimizing the equalizer jointly with a pattern-eliminating code. Although the performance of a pattern-eliminating code is given by a closed-form expression, the channel memory and the low error rates of interest render accurate simulation of standard error-correcting codes impractical. This work proposes performance estimation techniques for coded high-speed links, based on the underlying regimes of operation. (cont)It also introduces an efficient algorithm for computing accurate marginal probability distributions of signals in a coded high-speed link. by Natasa Blitvic. S.M. 2008-11-07T18:56:22Z 2008-11-07T18:56:22Z 2007 2008 Thesis http://hdl.handle.net/1721.1/43050 243852047 eng M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 144 p. application/pdf Massachusetts Institute of Technology |
| spellingShingle | Electrical Engineering and Computer Science. Blitvic, Natasa Channel coding for high speed links |
| title | Channel coding for high speed links |
| title_full | Channel coding for high speed links |
| title_fullStr | Channel coding for high speed links |
| title_full_unstemmed | Channel coding for high speed links |
| title_short | Channel coding for high speed links |
| title_sort | channel coding for high speed links |
| topic | Electrical Engineering and Computer Science. |
| url | http://hdl.handle.net/1721.1/43050 |
| work_keys_str_mv | AT blitvicnatasa channelcodingforhighspeedlinks |