A micropower DSP for sensor applications

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.

Bibliographic Details
Main Author: Ickes, Nathan J. (Nathan Jeffrey), 1979-
Other Authors: Anantha P. Chandrakasan.
Format: Thesis
Language:eng
Published: Massachusetts Institute of Technology 2009
Subjects:
Online Access:http://hdl.handle.net/1721.1/44418
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author Ickes, Nathan J. (Nathan Jeffrey), 1979-
author2 Anantha P. Chandrakasan.
author_facet Anantha P. Chandrakasan.
Ickes, Nathan J. (Nathan Jeffrey), 1979-
author_sort Ickes, Nathan J. (Nathan Jeffrey), 1979-
collection MIT
description Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.
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spelling mit-1721.1/444182019-04-10T13:19:30Z A micropower DSP for sensor applications Micropower digital signal processing for sensor applications Ickes, Nathan J. (Nathan Jeffrey), 1979- Anantha P. Chandrakasan. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Electrical Engineering and Computer Science. Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008. Includes bibliographical references (p. 171-176). Ultra-low power systems, such as wireless microsensor networks or implanted medical devices, are driving the development of processors capable of performing increasingly complicated computations using mere microwatts of power. This thesis describes the design of a micropower DSP intended for medium bandwidth microsensor applications (such as acoustic sensing and tracking) which achieves 4 MIPS performance at 40 [mu]W (10 pJ per instruction) operating at 450 mV and fabricated in 90 nm CMOS. Energy efficiency optimizations include a custom CPU instruction set, a miniature instruction cache with a novel replacement strategy, hardware accelerator cores for FIR filter and FFT operations, and extensive power gating of both logic and memory. The tradeoffs of cache size, line length, and replacement policy for very small (a few hundred words or less) caches are explored, as are the design implications of optimizing the cache for minimum energy without regard to performance (since onchip memory access is already single-cycle). A replacement policy designed to reduce thrashing in miniature instruction caches is presented. Efficient control of power-gated circuits requires consideration of the minimum off time, or break-even time. An energy model for determining the break-even time is developed, which correlates with measurements of the power-gated domains on the DSP. The energy savings obtained from hardware accelerators for FIR filtering and FFT operations are measured, and a model is developed to predict the actual net power reduction in a real system, including factors such as sampling rate, leakage power, latency requirements, and power gating overhead. by Nathan J. Ickes. Ph.D. 2009-01-30T16:44:25Z 2009-01-30T16:44:25Z 2008 2008 Thesis http://hdl.handle.net/1721.1/44418 289406261 eng M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 176 p. application/pdf Massachusetts Institute of Technology
spellingShingle Electrical Engineering and Computer Science.
Ickes, Nathan J. (Nathan Jeffrey), 1979-
A micropower DSP for sensor applications
title A micropower DSP for sensor applications
title_full A micropower DSP for sensor applications
title_fullStr A micropower DSP for sensor applications
title_full_unstemmed A micropower DSP for sensor applications
title_short A micropower DSP for sensor applications
title_sort micropower dsp for sensor applications
topic Electrical Engineering and Computer Science.
url http://hdl.handle.net/1721.1/44418
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