Mitigating timing noise in ADCs through digital post-processing
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.
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| Format: | Thesis |
| Language: | eng |
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Massachusetts Institute of Technology
2009
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| Online Access: | http://hdl.handle.net/1721.1/45749 |
| _version_ | 1826214089579298816 |
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| author | Weller, Daniel (Daniel Stuart) |
| author2 | Vivek K. Goyal. |
| author_facet | Vivek K. Goyal. Weller, Daniel (Daniel Stuart) |
| author_sort | Weller, Daniel (Daniel Stuart) |
| collection | MIT |
| description | Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008. |
| first_indexed | 2024-09-23T15:59:39Z |
| format | Thesis |
| id | mit-1721.1/45749 |
| institution | Massachusetts Institute of Technology |
| language | eng |
| last_indexed | 2024-09-23T15:59:39Z |
| publishDate | 2009 |
| publisher | Massachusetts Institute of Technology |
| record_format | dspace |
| spelling | mit-1721.1/457492019-04-11T02:54:04Z Mitigating timing noise in ADCs through digital post-processing Mitigating timing noise in analog-to-digital converters through digital post-processing Weller, Daniel (Daniel Stuart) Vivek K. Goyal. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Electrical Engineering and Computer Science. Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008. Includes bibliographical references (p. 91-93). The accuracy of analog-to-digital converters (ADCs) is greatly affected by the uniformity of the times at which samples of the analog input signal are taken. The error in the sample times, known as jitter, or timing noise, has a non-linear, time-varying and input-dependent effect on the sample values, as opposed to the additive noise usually considered. At present, the error due to jitter is minimized through the use of low-jitter clocks, limiting the suitability of such ADCs for low-power applications. This thesis investigates the problem of mitigating the effects of jitter through digital post-processing of the samples, which would allow ADCs to use less accurate clocks without compromising accuracy. This thesis equates mitigating jitter with estimating the parameters of a bandlimited input signal based on samples collected in the presence of timing noise. Two approaches are considered: classical, observation model-driven estimation, and Bayesian estimation that incorporates a prior model of the signal parameters. For both approaches, algorithms are derived that achieve lower mean-squared-error (MSE) by taking the non-linear effect of the jitter into account. In the non-random case, iterative approximations to the maximum likelihood estimator are developed, including an Expectation-Maximization algorithm. To bound the MSE of such algorithms, the unbiased Cram r-Rao lower bound is approximated using Gauss-Hermite quadrature. For the Bayesian approach, a Taylor series-based estimator and several variants on the Gibbs sampler that all approach the Bayes least squares estimate are designed. These estimators are compared in performance to the optimal linear estimators derived without taking jitter into account. (cont.) The proposed algorithms are shown to tolerate significantly more jitter than the baseline linear algorithms. Applications of these results and extending these algorithms to correcting spatial uncertainty are discussed briefly as well. by Daniel Weller. S.M. 2009-06-30T16:11:14Z 2009-06-30T16:11:14Z 2008 2008 Thesis http://hdl.handle.net/1721.1/45749 298125850 eng M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 93 p. application/pdf Massachusetts Institute of Technology |
| spellingShingle | Electrical Engineering and Computer Science. Weller, Daniel (Daniel Stuart) Mitigating timing noise in ADCs through digital post-processing |
| title | Mitigating timing noise in ADCs through digital post-processing |
| title_full | Mitigating timing noise in ADCs through digital post-processing |
| title_fullStr | Mitigating timing noise in ADCs through digital post-processing |
| title_full_unstemmed | Mitigating timing noise in ADCs through digital post-processing |
| title_short | Mitigating timing noise in ADCs through digital post-processing |
| title_sort | mitigating timing noise in adcs through digital post processing |
| topic | Electrical Engineering and Computer Science. |
| url | http://hdl.handle.net/1721.1/45749 |
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