Techniques for high-performance digital frequency synthesis and phase control
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.
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| Format: | Thesis |
| Language: | eng |
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Massachusetts Institute of Technology
2009
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| Online Access: | http://hdl.handle.net/1721.1/45870 |
| _version_ | 1826202775800774656 |
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| author | Hsu, Chun-Ming, Ph. D. Massachusetts Institute of Technology |
| author2 | Michael H. Perrott. |
| author_facet | Michael H. Perrott. Hsu, Chun-Ming, Ph. D. Massachusetts Institute of Technology |
| author_sort | Hsu, Chun-Ming, Ph. D. Massachusetts Institute of Technology |
| collection | MIT |
| description | Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008. |
| first_indexed | 2024-09-23T12:18:31Z |
| format | Thesis |
| id | mit-1721.1/45870 |
| institution | Massachusetts Institute of Technology |
| language | eng |
| last_indexed | 2024-09-23T12:18:31Z |
| publishDate | 2009 |
| publisher | Massachusetts Institute of Technology |
| record_format | dspace |
| spelling | mit-1721.1/458702019-04-11T01:47:22Z Techniques for high-performance digital frequency synthesis and phase control Hsu, Chun-Ming, Ph. D. Massachusetts Institute of Technology Michael H. Perrott. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Electrical Engineering and Computer Science. Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008. Includes bibliographical references (p. 183-190). This thesis presents a 3.6-GHz, 500-kHz bandwidth digital [delta][sigma] frequency synthesizer architecture that leverages a recently invented noise-shaping time-to-digital converter (TDC) and an all-digital quantization noise cancellation technique to achieve excellent in-band and out-of-band phase noise, respectively. In addition, a passive digital-to-analog converter (DAC) structure is proposed as an efficient interface between the digital loop filter and a conventional hybrid voltage-controlled oscillator (VCO) to create a digitally-controlled oscillator (DCO). An asynchronous divider structure is presented which lowers the required TDC range and avoids the divide-value-dependent delay variation. The prototype is implemented in a 0.13-am CMOS process and its active area occupies 0.95 mm². Operating under 1.5 V, the core parts, excluding the VCO output buffer, dissipate 26 mA. Measured phase noise at 3.67 GHz achieves -108 dBc/Hz and -150 dBc/Hz at 400 kHz and 20 MHz, respectively. Integrated phase noise at this carrier frequency yields 204 fs of jitter (measured from 1 kHz to 40 MHz). In addition, a 3.2-Gb/s delay-locked loop (DLL) in a 0.18-[mu]m CMOS for chip-tochip communications is presented. By leveraging the fractional-N synthesizer technique, this architecture provides a digitally-controlled delay adjustment with a fine resolution and infinite range. The provided delay resolution is less sensitive to the process, voltage, and temperature variations than conventional techniques. A new [delta][sigma] modulator enables a compact and low-power implementation of this architecture. A simple bang-bang detector is used for phase detection. The prototype operates at a 1.8-V supply voltage with a current consumption of 55 mA. The phase resolution and differential rms clock jitter are 1.4 degrees and 3.6 ps, respectively. by Chun-Ming Hsu. Ph.D. 2009-06-30T16:29:20Z 2009-06-30T16:29:20Z 2008 2008 Thesis http://hdl.handle.net/1721.1/45870 320092640 eng M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 190 p. application/pdf Massachusetts Institute of Technology |
| spellingShingle | Electrical Engineering and Computer Science. Hsu, Chun-Ming, Ph. D. Massachusetts Institute of Technology Techniques for high-performance digital frequency synthesis and phase control |
| title | Techniques for high-performance digital frequency synthesis and phase control |
| title_full | Techniques for high-performance digital frequency synthesis and phase control |
| title_fullStr | Techniques for high-performance digital frequency synthesis and phase control |
| title_full_unstemmed | Techniques for high-performance digital frequency synthesis and phase control |
| title_short | Techniques for high-performance digital frequency synthesis and phase control |
| title_sort | techniques for high performance digital frequency synthesis and phase control |
| topic | Electrical Engineering and Computer Science. |
| url | http://hdl.handle.net/1721.1/45870 |
| work_keys_str_mv | AT hsuchunmingphdmassachusettsinstituteoftechnology techniquesforhighperformancedigitalfrequencysynthesisandphasecontrol |