Analog to digital converters for CMOS imagers

Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1998.

Bibliographic Details
Main Author: Dacy, Susan (Susan Mary), 1975-
Other Authors: Charles Sodini and Marc Loinaz.
Format: Thesis
Language:eng
Published: Massachusetts Institute of Technology 2009
Subjects:
Online Access:http://hdl.handle.net/1721.1/46276
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author Dacy, Susan (Susan Mary), 1975-
author2 Charles Sodini and Marc Loinaz.
author_facet Charles Sodini and Marc Loinaz.
Dacy, Susan (Susan Mary), 1975-
author_sort Dacy, Susan (Susan Mary), 1975-
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description Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1998.
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spelling mit-1721.1/462762019-04-12T16:00:58Z Analog to digital converters for CMOS imagers A/D converters for CMOS imagers Dacy, Susan (Susan Mary), 1975- Charles Sodini and Marc Loinaz. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Electrical Engineering and Computer Science. Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1998. Includes bibliographical references (leaves 80-82). A/D converters for single chip CMOS imagers have often been designed using the column-parallel approach, employing a slow A/D converter for each column of the sensor array. This thesis investigates a serial approach utilizing a single fast A/D converter to process all of the imager pixels. If power scales linearly with frequency in a given A/D architecture, power dissipation for the two approaches should be comparable. However, the serial approach should occupy less area since only the cost of one A/D converter is incurred. A figure of merit 1/power*area is introduced to verify this theory by comparing previously reported A/D approaches after appropriate technology, speed, and supply scaling. Camera system specifications require a single serial A/D converter to have 10b resolution at a 3MHz sampling rate for a CIF (352x288) imager array running at 30 frames/second Area minimization, power minimization, and the ability to build the A/D in a standard CMOS process are extremely important for consumer product applications. A single slope A/D architecture with a subnanosecond time digitizer shows promise for optimizing figure of merit over pipelined and folding interpolating approaches. This work focuses on the design issues of the 3MHz single-slope based A/D converter. Architectures appropriate for extending this A/D converter to 12MHz for four times CIF image arrays (704x576) are discussed. The 3MHz converter was designed, simulated, and laid out in a 0.35um CMOS technology. At 3.3V supply, 25°C and nominal process conditions, the converter dissipates 29 mW while occupying 0.3 mm2 . A 12MHz trislope extension of this converter is estimated to dissipate 37 mW in 0.4 mm2. by Susan Dacy. M.Eng. 2009-06-30T18:47:01Z 2009-06-30T18:47:01Z 1998 1998 Thesis http://hdl.handle.net/1721.1/46276 47095231 eng M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 82 leaves application/pdf Massachusetts Institute of Technology
spellingShingle Electrical Engineering and Computer Science.
Dacy, Susan (Susan Mary), 1975-
Analog to digital converters for CMOS imagers
title Analog to digital converters for CMOS imagers
title_full Analog to digital converters for CMOS imagers
title_fullStr Analog to digital converters for CMOS imagers
title_full_unstemmed Analog to digital converters for CMOS imagers
title_short Analog to digital converters for CMOS imagers
title_sort analog to digital converters for cmos imagers
topic Electrical Engineering and Computer Science.
url http://hdl.handle.net/1721.1/46276
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