Micro-architectural analysis of SPACERAM processing element
Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1998.
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| Format: | Thesis |
| Language: | eng |
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Massachusetts Institute of Technology
2009
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| Online Access: | http://hdl.handle.net/1721.1/47717 |
| _version_ | 1826193301830631424 |
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| author | Pant, Amrit R. (Amrit Raj), 1971- |
| author2 | Thomas F. Knight, Jr. |
| author_facet | Thomas F. Knight, Jr. Pant, Amrit R. (Amrit Raj), 1971- |
| author_sort | Pant, Amrit R. (Amrit Raj), 1971- |
| collection | MIT |
| description | Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1998. |
| first_indexed | 2024-09-23T09:36:49Z |
| format | Thesis |
| id | mit-1721.1/47717 |
| institution | Massachusetts Institute of Technology |
| language | eng |
| last_indexed | 2024-09-23T09:36:49Z |
| publishDate | 2009 |
| publisher | Massachusetts Institute of Technology |
| record_format | dspace |
| spelling | mit-1721.1/477172019-04-11T10:33:38Z Micro-architectural analysis of SPACERAM processing element Pant, Amrit R. (Amrit Raj), 1971- Thomas F. Knight, Jr. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science Electrical Engineering and Computer Science Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1998. Includes bibliographical references (leaf 71). SPACERAM is a SIMD architecture optimized for symbolic spatial computations implemented with multiple banks of DRAM combined with an array of processing elements. Such an architecture facilitates very high processor-memory bandwidth and hence allows for applications requiring orders of magnitude higher processing and update rates per DRAM than any current hardware. The array of processing elements process data coming simultaneously from several memory blocks by applying appropriate shifting and lookup table updates to them. Every processing element contains a permuter which makes it possible to assign data bits from any DRAM block to any functional block within the processing element as specified by controller setup. The lookup table is implemented as a common bus shared by all the processing elements. Micro-architectural analysis of such a processing element presents various possible implementations and trade-off issues associated with them. by Amrit R. Pant. M.Eng. 2009-10-01T15:34:48Z 2009-10-01T15:34:48Z 1998 1998 Thesis http://hdl.handle.net/1721.1/47717 42429570 eng M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 72 leaves application/pdf Massachusetts Institute of Technology |
| spellingShingle | Electrical Engineering and Computer Science Pant, Amrit R. (Amrit Raj), 1971- Micro-architectural analysis of SPACERAM processing element |
| title | Micro-architectural analysis of SPACERAM processing element |
| title_full | Micro-architectural analysis of SPACERAM processing element |
| title_fullStr | Micro-architectural analysis of SPACERAM processing element |
| title_full_unstemmed | Micro-architectural analysis of SPACERAM processing element |
| title_short | Micro-architectural analysis of SPACERAM processing element |
| title_sort | micro architectural analysis of spaceram processing element |
| topic | Electrical Engineering and Computer Science |
| url | http://hdl.handle.net/1721.1/47717 |
| work_keys_str_mv | AT pantamritramritraj1971 microarchitecturalanalysisofspaceramprocessingelement |