Generating efficient layouts from optimized MOS circuit schematics
Also issued as Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1988.
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| 語言: | eng |
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Research Laboratory of Electronics, Massachusetts Institute of Technology
2004
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| 在線閱讀: | http://hdl.handle.net/1721.1/4957 |
| 總結: | Also issued as Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1988. |
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