Generating efficient layouts from optimized MOS circuit schematics
Also issued as Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1988.
| Other Authors: | |
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| Language: | eng |
| Published: |
Research Laboratory of Electronics, Massachusetts Institute of Technology
2004
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| Online Access: | http://hdl.handle.net/1721.1/4957 |
| _version_ | 1826215132454191104 |
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| author2 | Baltus, Donald George. |
| author_facet | Baltus, Donald George. |
| collection | MIT |
| description | Also issued as Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1988. |
| first_indexed | 2024-09-23T16:17:05Z |
| id | mit-1721.1/4957 |
| institution | Massachusetts Institute of Technology |
| language | eng |
| last_indexed | 2024-09-23T16:17:05Z |
| publishDate | 2004 |
| publisher | Research Laboratory of Electronics, Massachusetts Institute of Technology |
| record_format | dspace |
| spelling | mit-1721.1/49572019-04-12T08:18:58Z Generating efficient layouts from optimized MOS circuit schematics Baltus, Donald George. TK7855.M41 R43 no.535 Also issued as Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1988. Includes bibliographical references. Supported by the U.S. Air Force--Office of Scientific Research. AFOSR-86-0164 Supported in part by a National Science Foundation Graduate Fellowship. Supported in part by Thinking Machines Corporation. 2305/B4 Donald George Baltus. 2004-03-03T22:15:29Z 2004-03-03T22:15:29Z 1988 no. 535 http://hdl.handle.net/1721.1/4957 eng Technical report (Massachusetts Institute of Technology. Research Laboratory of Electronics) ; 535. ix, 194 p. 10316361 bytes application/pdf application/pdf Research Laboratory of Electronics, Massachusetts Institute of Technology |
| spellingShingle | TK7855.M41 R43 no.535 Generating efficient layouts from optimized MOS circuit schematics |
| title | Generating efficient layouts from optimized MOS circuit schematics |
| title_full | Generating efficient layouts from optimized MOS circuit schematics |
| title_fullStr | Generating efficient layouts from optimized MOS circuit schematics |
| title_full_unstemmed | Generating efficient layouts from optimized MOS circuit schematics |
| title_short | Generating efficient layouts from optimized MOS circuit schematics |
| title_sort | generating efficient layouts from optimized mos circuit schematics |
| topic | TK7855.M41 R43 no.535 |
| url | http://hdl.handle.net/1721.1/4957 |