Generating efficient layouts from optimized MOS circuit schematics

Generating efficient layouts from optimized MOS circuit schematics

Also issued as Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1988.

Bibliographic Details
Other Authors:	Baltus, Donald George.
Language:	eng
Published:	Research Laboratory of Electronics, Massachusetts Institute of Technology 2004
Subjects:	TK7855.M41 R43 no.535
Online Access:	http://hdl.handle.net/1721.1/4957

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