A 12b, 50 MS/s, Fully Differential Zero-Crossing Based Pipelined ADC
Zero-crossing based switch capacitor circuits have been introduced as alternatives to op-amp based circuits for eased design considerations and improved power efficiency. This work further improves the resolution, power efficiency, and robustness of previous zero-crossing based circuits (ZCBCs) and...
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| 格式: | 文件 |
| 语言: | en_US |
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Institute of Electrical and Electronics Engineers
2010
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| 主题: | |
| 在线阅读: | http://hdl.handle.net/1721.1/52575 https://orcid.org/0000-0002-7783-0403 |
| _version_ | 1826213972475379712 |
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| author | Brooks, Lane Lee, Hae-Seung |
| author2 | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science |
| author_facet | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science Brooks, Lane Lee, Hae-Seung |
| author_sort | Brooks, Lane |
| collection | MIT |
| description | Zero-crossing based switch capacitor circuits have been introduced as alternatives to op-amp based circuits for eased design considerations and improved power efficiency. This work further improves the resolution, power efficiency, and robustness of previous zero-crossing based circuits (ZCBCs) and features a 90 nm CMOS, offset compensated, fully differential, zero-crossing based, 12b, 50 MS/s, pipelined ADC requiring no CMFB. The power consumption is 4.5 mW. The FOM is 88 fJ/step. Fully differential signaling is used to improve power supply rejection and power efficiency. A power efficient chopping offset compensation technique is presented. Reference voltage switching is improved to avoid gate boosted switches. Redundancy is used to reduce output range requirements for increased signal range. Two regenerative latch architectures used for bit decision comparison are analyzed and measured for offset, noise, and speed. |
| first_indexed | 2024-09-23T15:57:46Z |
| format | Article |
| id | mit-1721.1/52575 |
| institution | Massachusetts Institute of Technology |
| language | en_US |
| last_indexed | 2024-09-23T15:57:46Z |
| publishDate | 2010 |
| publisher | Institute of Electrical and Electronics Engineers |
| record_format | dspace |
| spelling | mit-1721.1/525752024-07-12T20:12:36Z A 12b, 50 MS/s, Fully Differential Zero-Crossing Based Pipelined ADC Brooks, Lane Lee, Hae-Seung Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science Lee, Hae-Seung Brooks, Lane Lee, Hae-Seung zero-crossing based circuits scaled CMOS offset compensation comparator-based switched-capacitor circuits chopping chopper stabilization ZCBC CHS CBSC ADC A/D Zero-crossing based switch capacitor circuits have been introduced as alternatives to op-amp based circuits for eased design considerations and improved power efficiency. This work further improves the resolution, power efficiency, and robustness of previous zero-crossing based circuits (ZCBCs) and features a 90 nm CMOS, offset compensated, fully differential, zero-crossing based, 12b, 50 MS/s, pipelined ADC requiring no CMFB. The power consumption is 4.5 mW. The FOM is 88 fJ/step. Fully differential signaling is used to improve power supply rejection and power efficiency. A power efficient chopping offset compensation technique is presented. Reference voltage switching is improved to avoid gate boosted switches. Redundancy is used to reduce output range requirements for increased signal range. Two regenerative latch architectures used for bit decision comparison are analyzed and measured for offset, noise, and speed. Massachusetts Institute of Technology. Center for Integrated Circuits and Systems National Defense Science and Engineering Graduate Fellowship Defence Advanced Research Projects Agency (Grant N66001-06-2046) 2010-03-15T14:57:34Z 2010-03-15T14:57:34Z 2009-12 2009-08 Article http://purl.org/eprint/type/JournalArticle 0018-9200 http://hdl.handle.net/1721.1/52575 Brooks, L., and Hae-Seung Lee. “A 12b, 50 MS/s, Fully Differential Zero-Crossing Based Pipelined ADC.” Solid-State Circuits, IEEE Journal of 44.12 (2009): 3329-3343. © 2009 IEEE https://orcid.org/0000-0002-7783-0403 en_US http://dx.doi.org/10.1109/JSSC.2009.2032639 IEEE Journal of Solid-State Circuits Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use. application/pdf Institute of Electrical and Electronics Engineers IEEE |
| spellingShingle | zero-crossing based circuits scaled CMOS offset compensation comparator-based switched-capacitor circuits chopping chopper stabilization ZCBC CHS CBSC ADC A/D Brooks, Lane Lee, Hae-Seung A 12b, 50 MS/s, Fully Differential Zero-Crossing Based Pipelined ADC |
| title | A 12b, 50 MS/s, Fully Differential Zero-Crossing Based Pipelined ADC |
| title_full | A 12b, 50 MS/s, Fully Differential Zero-Crossing Based Pipelined ADC |
| title_fullStr | A 12b, 50 MS/s, Fully Differential Zero-Crossing Based Pipelined ADC |
| title_full_unstemmed | A 12b, 50 MS/s, Fully Differential Zero-Crossing Based Pipelined ADC |
| title_short | A 12b, 50 MS/s, Fully Differential Zero-Crossing Based Pipelined ADC |
| title_sort | 12b 50 ms s fully differential zero crossing based pipelined adc |
| topic | zero-crossing based circuits scaled CMOS offset compensation comparator-based switched-capacitor circuits chopping chopper stabilization ZCBC CHS CBSC ADC A/D |
| url | http://hdl.handle.net/1721.1/52575 https://orcid.org/0000-0002-7783-0403 |
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