A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm CMOS
A compact and power-efficient serial I/O targeting dense silicon carrier interconnects is reported. Based on expected channel characteristics, the proposed I/O features low-impedance transmitter termination, high-impedance receiver termination, and a receiver with modified DFE with IIR filter feedba...
| Main Authors: | , , , , |
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| Format: | Article |
| Language: | en_US |
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Institute of Electrical and Electronics Engineers
2010
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| Online Access: | http://hdl.handle.net/1721.1/52716 |
| _version_ | 1811075198799052800 |
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| author | Kim, Byeong-Su Liu, Yong Dickson, Timothy O. Bulzacchelli, John F. Friedman, Daniel J. |
| author2 | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science |
| author_facet | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science Kim, Byeong-Su Liu, Yong Dickson, Timothy O. Bulzacchelli, John F. Friedman, Daniel J. |
| author_sort | Kim, Byeong-Su |
| collection | MIT |
| description | A compact and power-efficient serial I/O targeting dense silicon carrier interconnects is reported. Based on expected channel characteristics, the proposed I/O features low-impedance transmitter termination, high-impedance receiver termination, and a receiver with modified DFE with IIR filter feedback (DFE-IIR). The DFE-IIR receiver uses a single additional IIR filter feedback tap to compensate many post cursors without paying the power and area penalty that would be incurred with a conventional high tap-count DFE. Equalization capabilities of the compact I/O at 10 Gb/s are demonstrated over various channels including conventional chip-to-chip and backplane links with half-baud losses of up to 27 dB. Finally, a transmitter-receiver pair operating over a 40-mm on-chip emulated silicon carrier channel was demonstrated to 8.9 Gb/s, at a link power efficiency of 1.9 mW/Gb/s. |
| first_indexed | 2024-09-23T10:02:26Z |
| format | Article |
| id | mit-1721.1/52716 |
| institution | Massachusetts Institute of Technology |
| language | en_US |
| last_indexed | 2024-09-23T10:02:26Z |
| publishDate | 2010 |
| publisher | Institute of Electrical and Electronics Engineers |
| record_format | dspace |
| spelling | mit-1721.1/527162022-09-30T18:29:48Z A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm CMOS Kim, Byeong-Su Liu, Yong Dickson, Timothy O. Bulzacchelli, John F. Friedman, Daniel J. Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science Kim, Byeong-Su Kim, Byeong-Su backplane channel communication chip-to-chip communication compact I/O continuous-time IIR filter decision feedback equalizer serial link silicon carrier links A compact and power-efficient serial I/O targeting dense silicon carrier interconnects is reported. Based on expected channel characteristics, the proposed I/O features low-impedance transmitter termination, high-impedance receiver termination, and a receiver with modified DFE with IIR filter feedback (DFE-IIR). The DFE-IIR receiver uses a single additional IIR filter feedback tap to compensate many post cursors without paying the power and area penalty that would be incurred with a conventional high tap-count DFE. Equalization capabilities of the compact I/O at 10 Gb/s are demonstrated over various channels including conventional chip-to-chip and backplane links with half-baud losses of up to 27 dB. Finally, a transmitter-receiver pair operating over a 40-mm on-chip emulated silicon carrier channel was demonstrated to 8.9 Gb/s, at a link power efficiency of 1.9 mW/Gb/s. 2010-03-18T18:29:47Z 2010-03-18T18:29:47Z 2009-12 2009-06 Article http://purl.org/eprint/type/JournalArticle 0018-9200 INSPEC Accession Number: 11020424 http://hdl.handle.net/1721.1/52716 Byungsub Kim et al. “A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm CMOS.” Solid-State Circuits, IEEE Journal of 44.12 (2009): 3526-3538. © 2009 Institute of Electrical and Electronics Engineers en_US http://dx.doi.org/10.1109/jssc.2009.2031015 IEEE Journal of Solid-State Circuits Article is made available in accordance with the publisher’s policy and may be subject to US copyright law. Please refer to the publisher’s site for terms of use. application/pdf Institute of Electrical and Electronics Engineers IEEE |
| spellingShingle | backplane channel communication chip-to-chip communication compact I/O continuous-time IIR filter decision feedback equalizer serial link silicon carrier links Kim, Byeong-Su Liu, Yong Dickson, Timothy O. Bulzacchelli, John F. Friedman, Daniel J. A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm CMOS |
| title | A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm CMOS |
| title_full | A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm CMOS |
| title_fullStr | A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm CMOS |
| title_full_unstemmed | A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm CMOS |
| title_short | A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm CMOS |
| title_sort | 10 gb s compact low power serial i o with dfe iir equalization in 65 nm cmos |
| topic | backplane channel communication chip-to-chip communication compact I/O continuous-time IIR filter decision feedback equalizer serial link silicon carrier links |
| url | http://hdl.handle.net/1721.1/52716 |
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