A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm CMOS

A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm CMOS

Show other versions (1)

A compact and power-efficient serial I/O targeting dense silicon carrier interconnects is reported. Based on expected channel characteristics, the proposed I/O features low-impedance transmitter termination, high-impedance receiver termination, and a receiver with modified DFE with IIR filter feedba...

全面介绍

书目详细资料
Main Authors: Kim, Byeong-Su, Liu, Yong, Dickson, Timothy O., Bulzacchelli, John F., Friedman, Daniel J.
其他作者: Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
格式: 文件
语言:en_US
出版: Institute of Electrical and Electronics Engineers 2010
主题:
backplane channel communication
chip-to-chip communication
compact I/O
continuous-time IIR filter
decision feedback equalizer
serial link
silicon carrier links
在线阅读:http://hdl.handle.net/1721.1/52716

因特网

http://hdl.handle.net/1721.1/52716

相似书籍