A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm CMOS

A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm CMOS

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A compact and power-efficient serial I/O targeting dense silicon carrier interconnects is reported. Based on expected channel characteristics, the proposed I/O features low-impedance transmitter termination, high-impedance receiver termination, and a receiver with modified DFE with IIR filter feedba...

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Bibliographic Details
Main Authors: Kim, Byeong-Su, Liu, Yong, Dickson, Timothy O., Bulzacchelli, John F., Friedman, Daniel J.
Other Authors: Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Format: Article
Language:en_US
Published: Institute of Electrical and Electronics Engineers 2010
Subjects:
backplane channel communication
chip-to-chip communication
compact I/O
continuous-time IIR filter
decision feedback equalizer
serial link
silicon carrier links
Online Access:http://hdl.handle.net/1721.1/52716

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