A timeshared, runtime reconfigurable hardware co-processing architecture
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009.
| Main Author: | |
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| Other Authors: | |
| Format: | Thesis |
| Language: | eng |
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Massachusetts Institute of Technology
2010
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| Online Access: | http://hdl.handle.net/1721.1/53147 |
| _version_ | 1826197460902477824 |
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| author | Gelb, Benjamin S |
| author2 | Christopher J. Terman. |
| author_facet | Christopher J. Terman. Gelb, Benjamin S |
| author_sort | Gelb, Benjamin S |
| collection | MIT |
| description | Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009. |
| first_indexed | 2024-09-23T10:48:20Z |
| format | Thesis |
| id | mit-1721.1/53147 |
| institution | Massachusetts Institute of Technology |
| language | eng |
| last_indexed | 2024-09-23T10:48:20Z |
| publishDate | 2010 |
| publisher | Massachusetts Institute of Technology |
| record_format | dspace |
| spelling | mit-1721.1/531472019-04-11T13:42:04Z A timeshared, runtime reconfigurable hardware co-processing architecture Gelb, Benjamin S Christopher J. Terman. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Electrical Engineering and Computer Science. Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009. Includes bibliographical references (leaves 73-74). The constant desire for increased performance in microprocessor systems has led to the need for specialized hardware cores to accelerate specific computational tasks. In this thesis, we explore the potential of using FPGA partial reconfiguration to create a platform for customized hardware cores that may be loaded on demand, at runtime, and replaced when not in use. We implement two new software tools, bitparse and bitrender, to demonstrate the bitstream relocation technique. Further, we present a functional microprocessor system coupled with a runtime reprogramable peripheral synthesized on a Xilinx Virtex-5 FPGA and discuss its performance implications. by Benjamin S. Gelb. M.Eng. 2010-03-25T15:07:04Z 2010-03-25T15:07:04Z 2009 2009 Thesis http://hdl.handle.net/1721.1/53147 505532150 eng M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 74 leaves application/pdf Massachusetts Institute of Technology |
| spellingShingle | Electrical Engineering and Computer Science. Gelb, Benjamin S A timeshared, runtime reconfigurable hardware co-processing architecture |
| title | A timeshared, runtime reconfigurable hardware co-processing architecture |
| title_full | A timeshared, runtime reconfigurable hardware co-processing architecture |
| title_fullStr | A timeshared, runtime reconfigurable hardware co-processing architecture |
| title_full_unstemmed | A timeshared, runtime reconfigurable hardware co-processing architecture |
| title_short | A timeshared, runtime reconfigurable hardware co-processing architecture |
| title_sort | timeshared runtime reconfigurable hardware co processing architecture |
| topic | Electrical Engineering and Computer Science. |
| url | http://hdl.handle.net/1721.1/53147 |
| work_keys_str_mv | AT gelbbenjamins atimesharedruntimereconfigurablehardwarecoprocessingarchitecture AT gelbbenjamins timesharedruntimereconfigurablehardwarecoprocessingarchitecture |