Characterization and mitigation of process variation in digital circuits and systems
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009.
| Main Author: | |
|---|---|
| Other Authors: | |
| Format: | Thesis |
| Language: | eng |
| Published: |
Massachusetts Institute of Technology
2010
|
| Subjects: | |
| Online Access: | http://hdl.handle.net/1721.1/53271 |
| _version_ | 1826205187009675264 |
|---|---|
| author | Drego, Nigel Anthony, 1980- |
| author2 | Duane Boning and Anantha Chandrakasan. |
| author_facet | Duane Boning and Anantha Chandrakasan. Drego, Nigel Anthony, 1980- |
| author_sort | Drego, Nigel Anthony, 1980- |
| collection | MIT |
| description | Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009. |
| first_indexed | 2024-09-23T13:08:43Z |
| format | Thesis |
| id | mit-1721.1/53271 |
| institution | Massachusetts Institute of Technology |
| language | eng |
| last_indexed | 2024-09-23T13:08:43Z |
| publishDate | 2010 |
| publisher | Massachusetts Institute of Technology |
| record_format | dspace |
| spelling | mit-1721.1/532712019-04-10T13:48:46Z Characterization and mitigation of process variation in digital circuits and systems Drego, Nigel Anthony, 1980- Duane Boning and Anantha Chandrakasan. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Electrical Engineering and Computer Science. Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009. Cataloged from PDF version of thesis. Includes bibliographical references (p. 155-166). Process variation threatens to negate a whole generation of scaling in advanced process technologies due to performance and power spreads of greater than 30-50%. Mitigating this impact requires a thorough understanding of the variation sources, magnitudes and spatial components at the device, circuit and architectural levels. This thesis explores the impacts of variation at each of these levels and evaluates techniques to alleviate them in the context of digital circuits and systems. At the device level, we propose isolation and measurement of variation in the intrinsic threshold voltage of a MOSFET using sub-threshold leakage currents. Analysis of the measured data, from a test-chip implemented on a 0. 18[mu]m CMOS process, indicates that variation in MOSFET threshold voltage is a truly random process dependent only on device dimensions. Further decomposition of the observed variation reveals no systematic within-die variation components nor any spatial correlation. A second test-chip capable of characterizing spatial variation in digital circuits is developed and implemented in a 90nm triple-well CMOS process. Measured variation results show that the within-die component of variation is small at high voltages but is an increasing fraction of the total variation as power-supply voltage decreases. Once again, the data shows no evidence of within-die spatial correlation and only weak systematic components. Evaluation of adaptive body-biasing and voltage scaling as variation mitigation techniques proves voltage scaling is more effective in performance modification with reduced impact to idle power compared to body-biasing. (cont.) Finally, the addition of power-supply voltages in a massively parallel multicore processor is explored to reduce the energy required to cope with process variation. An analytic optimization framework is developed and analyzed; using a custom simulation methodology, total energy of a hypothetical 1K-core processor based on the RAW core is reduced by 6-16% with the addition of only a single voltage. Analysis of yield versus required energy demonstrates that a combination of disabling poor-performing cores and additional power-supply voltages results in an optimal trade-off between performance and energy. by Nigel Anthony Drego. Ph.D. 2010-03-25T15:23:56Z 2010-03-25T15:23:56Z 2009 2009 Thesis http://hdl.handle.net/1721.1/53271 547178639 eng M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 166 p. application/pdf Massachusetts Institute of Technology |
| spellingShingle | Electrical Engineering and Computer Science. Drego, Nigel Anthony, 1980- Characterization and mitigation of process variation in digital circuits and systems |
| title | Characterization and mitigation of process variation in digital circuits and systems |
| title_full | Characterization and mitigation of process variation in digital circuits and systems |
| title_fullStr | Characterization and mitigation of process variation in digital circuits and systems |
| title_full_unstemmed | Characterization and mitigation of process variation in digital circuits and systems |
| title_short | Characterization and mitigation of process variation in digital circuits and systems |
| title_sort | characterization and mitigation of process variation in digital circuits and systems |
| topic | Electrical Engineering and Computer Science. |
| url | http://hdl.handle.net/1721.1/53271 |
| work_keys_str_mv | AT dregonigelanthony1980 characterizationandmitigationofprocessvariationindigitalcircuitsandsystems |