Theory of composable latency-insensitive refinements
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009.
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| Format: | Thesis |
| Language: | eng |
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Massachusetts Institute of Technology
2010
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| Online Access: | http://hdl.handle.net/1721.1/53319 |
| _version_ | 1826192420742627328 |
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| author | Vijayaraghavan, Muralidaran |
| author2 | Arvind. |
| author_facet | Arvind. Vijayaraghavan, Muralidaran |
| author_sort | Vijayaraghavan, Muralidaran |
| collection | MIT |
| description | Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009. |
| first_indexed | 2024-09-23T09:11:45Z |
| format | Thesis |
| id | mit-1721.1/53319 |
| institution | Massachusetts Institute of Technology |
| language | eng |
| last_indexed | 2024-09-23T09:11:45Z |
| publishDate | 2010 |
| publisher | Massachusetts Institute of Technology |
| record_format | dspace |
| spelling | mit-1721.1/533192019-04-10T17:59:52Z Theory of composable latency-insensitive refinements Vijayaraghavan, Muralidaran Arvind. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Electrical Engineering and Computer Science. Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009. Cataloged from PDF version of thesis. Includes bibliographical references (p. 36-37). Simulation of a synchronous system on a hardware platform, for example an FPGA, can be performed using a hardware prototype of the system. But the prototype may not meet the resource and timing constraints of that platform. One way to meet the constraints is to partition the prototype hierarchically into modules, and to refine the individual modules while preserving the overall behavior of the system. In this thesis we formalize the notion of a refinement that preserves the behavior of the original modules - we call such refinements latency-insensitive refinements. We show that if these latency-insensitive refinements of the modules obey certain conditions, then these refinements can be composed together hierarchically in order to obtain the latency-insensitive refinement of the original system. We call the latency-insensitive refinements that obey these conditions as composable latency-insensitive refinements. We also give a procedure to automatically transform a module to a latency-insensitive refinement while obeying the conditions that enable it to be composed hierarchically. The transformation serves as a starting point for making further refinements and optimizations, and thus, gives a methodology to design hardware simulators for synchronous systems. by Muralidaran Vijayaraghavan. S.M. 2010-03-25T15:30:52Z 2010-03-25T15:30:52Z 2009 2009 Thesis http://hdl.handle.net/1721.1/53319 550571316 eng M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 37 p. application/pdf Massachusetts Institute of Technology |
| spellingShingle | Electrical Engineering and Computer Science. Vijayaraghavan, Muralidaran Theory of composable latency-insensitive refinements |
| title | Theory of composable latency-insensitive refinements |
| title_full | Theory of composable latency-insensitive refinements |
| title_fullStr | Theory of composable latency-insensitive refinements |
| title_full_unstemmed | Theory of composable latency-insensitive refinements |
| title_short | Theory of composable latency-insensitive refinements |
| title_sort | theory of composable latency insensitive refinements |
| topic | Electrical Engineering and Computer Science. |
| url | http://hdl.handle.net/1721.1/53319 |
| work_keys_str_mv | AT vijayaraghavanmuralidaran theoryofcomposablelatencyinsensitiverefinements |