| Summary: | We report a programmable analog bionic ear (cochlear implant) processor in a 1.5µm BiCMOS technology with a power
consumption of 211µW and 77dB dynamic range of operation. The 9.58mm x 9.23mm processor chip runs on a 2.8V supply and has a
power consumption that is lower than state-of-the-art A/D-then-DSP designs by a factor of 25. It is suitable for use in fully implanted
cochlear-implant systems of the future which require decades of operation on a 100mAh rechargeable battery with a finite number of
charge-discharge cycles. It may also be used as an ultra-low-power spectrum-analysis front end in portable speech-recognition
systems. The power consumption of the processor includes the 100µW power consumption of a JFET-buffered electret microphone
and an associated on-chip microphone front end. An automatic gain control circuit compresses the 77dB input dynamic range into a
narrower internal dynamic range (IDR) of 57dB at which each of the 16 spectral channels of the processor operate. Each of these
channels is made up of a bandpass filter with programmable low and high corner frequencies, an envelope detector with
programmable attack and release times, and a logarithmic dual-slope analog-to-digital converter with programmable offsetcalibration
and sampling-rate parameters. The output bits of the processor are scanned and reported off chip in a format suitable for
continuous-interleaved-sampling (CIS) stimulation of electrodes. Power-supply-insensitive biasing and circuit design provide robust
operation of the processor in the high-RF-noise environment of current cochlear-implant systems. Constant-Gm subthreshold MOS
biasing, current-reference distribution, and feedforward and feedback offset-calibration are used to combat the effects of temperature
and transistor mismatch. The processing power of this processor is below that of a very low power microphone-and-A/D front end
alone. Thus, even zero digital power consumption will likely make an A/D-then-DSP design consume more power than this processor
at the end of Moore’s law one or two decades in the future. This design suggests that the current trend of digitizing analog information
at high-speed and high precision as soon as possible followed by processing in the digital domain is not an efficient solution if power
consumption is of paramount importance. Rather, it is more advantageous to do robust-and-programmable analog preprocessing and
digitize higher-level information at lower speed and lower precision
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